Charge sharing in dynamic logic?

CTho9305

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Jul 26, 2000
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Why is charge redistribution a problem in dynamic logic? If you wait long enough, shouldn't the output eventually correct itself? Is it only a problem if you are concerned with hazards/glitches? Why it is worse for dynamic logic to switch values more than once before settling? Slow pull-up if it does get pulled down temporarily?
 

sgtroyer

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Feb 14, 2000
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The thing about dynamic logic is, glitches are never okay. In the evaluate phase, once a node has been discharged, it can't be recharged. Unlike static CMOS, where a glitch will toggle but settle back to the correct value, in dynamic CMOS once it toggles it's stuck. There's no such thing as switching values more than once before settling.
 

CTho9305

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Jul 26, 2000
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Ah, I went back and looked at some dynamic circuits and see now that I was misreading them. I guess I didn't pay enough attention to dynamic logic vs. pseudo-nmos. The PMOS pullup is clocked in the dynamic logic, so that makes sense that you can't pull the output up once the clock changes :).

Glitches are not catastrophic in pseudo-nmos though, right? (My original confusion arose because I wasn't paying attention to what the pmos transistor's gate was connected to.)

edit: Cool, this PPT goes through the book I'm reading. He even stole his pictures from it :). Now I can check another explanation of the material before asking more questions that make me look stupid ;).
 

sgtroyer

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Feb 14, 2000
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That's right, pseudo-nmos is similar to CMOS, it can handle glitches. The difference, like you said, is that the pfet is always on in pseudo-nmos. IMO pseudo-nmos is easier to design in than dynamic CMOS. It's more robust wrt noise etc. It uses a lot of static power, though, so it's not practical for widespread use on a large chip.