- Dec 12, 2000
- 25,594
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Holy crap!
Read this and check teh pix0rz!!
:Q
Highlights:
- The version expected to power the Playstation 3 has a 221mm² die, uses 234 million transistors and is made using 90nm process technology.
- 8x64-bit floating point processors, referred to as synergistic processor elements (SPEs). - 1x64-bit Power processor capable of running two threads.
- SPEs take 128-bit operands, split into four 32-bit words. Up to 128 operands can be stored in the register file.
- Each 2.5x5.81mm SPE can issue two instructions per cycle to seven execution units using two pipelines. There is no out of order execution. [<- built for streaming media?]
- Element Interconnect Bus (EIB), comprising four 128-bit rings and a 64-bit tag running at half the processor clock ties everything together.
- Busses connect to SPEs through local memory, 256kbyte for each SPE. The developers have tested the memories to 5.4GHz at 1.3V and 52°C.
- There are 15 separate power domains on the chip. Ten digital thermometers monitor the chip at various points to alert the system of thermal problems.
I have no idea what all this means...when will Anand have his preview article up?
**UPDATE**
Other articles have said that the prototype and the version powering PS3 are NOT the same chip! The PS3 Cell will NOT run at 4GHz and will likely have 6 SPEs vs. 8. While 4GHz is theoretically possible, analysts expect PS3's Cell to run between 2-3GHz.
Read this and check teh pix0rz!!
:Q
Highlights:
- The version expected to power the Playstation 3 has a 221mm² die, uses 234 million transistors and is made using 90nm process technology.
- 8x64-bit floating point processors, referred to as synergistic processor elements (SPEs). - 1x64-bit Power processor capable of running two threads.
- SPEs take 128-bit operands, split into four 32-bit words. Up to 128 operands can be stored in the register file.
- Each 2.5x5.81mm SPE can issue two instructions per cycle to seven execution units using two pipelines. There is no out of order execution. [<- built for streaming media?]
- Element Interconnect Bus (EIB), comprising four 128-bit rings and a 64-bit tag running at half the processor clock ties everything together.
- Busses connect to SPEs through local memory, 256kbyte for each SPE. The developers have tested the memories to 5.4GHz at 1.3V and 52°C.
- There are 15 separate power domains on the chip. Ten digital thermometers monitor the chip at various points to alert the system of thermal problems.
I have no idea what all this means...when will Anand have his preview article up?
**UPDATE**
Other articles have said that the prototype and the version powering PS3 are NOT the same chip! The PS3 Cell will NOT run at 4GHz and will likely have 6 SPEs vs. 8. While 4GHz is theoretically possible, analysts expect PS3's Cell to run between 2-3GHz.
