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someone told me it had half of the math processor, is this right? as far as i knew, the celeron was a PIII with half the L2 cache, 4 way associative L2 instead of the PIII's 8 way, and it ran on a 66mhz bus instead of 100 or 133
The new celerons are actually EXACTLY the same as a PIII with the SMP circuitry and half the L2 cache physically BURNED out of the CPU.
They do it for economic reasons- They've determined it would be cheaper to do this- I guess because of the bin curves of the coppermine core. If they didn't, they would be trashing lots of 500-650mhz cores that would otherwise be saturating the PIII market.
funny, i seem to remember an article by Anand saying thet the new celerons where a different production run, and not coppermine cpu's with half the l2 cache disabled/burned/manipulated?
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