The new celerons are actually EXACTLY the same as a PIII with the SMP circuitry and half the L2 cache physically BURNED out of the CPU.
They do it for economic reasons- They've determined it would be cheaper to do this- I guess because of the bin curves of the coppermine core. If they didn't, they would be trashing lots of 500-650mhz cores that would otherwise be saturating the PIII market.
Eric