CAS timings 2 vs 2.5 vs 3

[Jittles]

I was wondering, there are no CAS 2.5 SDRAM chips that i've seen, only DDR.

Wouldn't the DDR at 2.5 still have to finish the 3rd cycle or whatever to continue?
Or can DDR start on the falling edge newly again?

Or maybe I just don't understand what all that means?

 

[DeeK]

DDR can have 2.5 CL because it's two clocks per cycle. The CAS latency is the time, measured in clock cycles, between the time the address is registered and the time the data first appears on the data bus. CAS latency on both SDR and DDR are measured in terms of the clock rate, not the edge rate. In SDR memory, CAS latency of 2 means the data appears more than one clock edge after the address is registered, but before the second edge happens. CAS latency of 2.5 in DDR means the data appears after the fourth edge (this counts both positive and negative edges) and before the fifth edge. If DDR were measured by edge rate, then it'd be CAS 5 DDR, which doesn't look good on the marketing materials.