Not sure on the % difference... it would actually vary with the applicatoin. But basically CAS latency is the result of the structure of SDRAM - the memory is laid out in rows/columns. To read a certain location, you have to precharge a line, and once it is charged, read from the cell you want. Now, the benefit of SDRAM is that once you charge a column and read, it will also give you the rest of the column (Or something like that) since there is a high probability that you will need that data soon also (due to "spatial locality" - BurntKooshie can explain that better).
So... I would imagine that if you wrote something that only used one byte from each column, then the next cycle read from a different column, there might be a 50% difference. However, I would also imagine that this would be pretty difficult to pull off
edit: i'm sure
BK's article mentions something about spatial locality
