Can you guys give me info on the on-chip memory controller for some AMD CPU's?

[blurredvision]

In my A+ class over the weekend (just started), the teacher was talking about the northbridge and bus speeds and such. I asked for what he knew about the new AMD CPU's and how some chips now have the memory controller built onto the chip itself. He didn't know what I was talking about, and asked me to get some more info for him about it so he could educate himself.

Unfortunately, I've never looked into it much, and what I posted above is as far as my knowledge goes. Can you guys help me with some info on exactly which chips and/or sockets the memory controller is built onto? Does this help with hypertransport speeds, and what are the current speeds of hypertransport? Doesn't this also completely remove the northbridge from some chipsets?

Thanks guys.

 

[DaveSimmons]

Check ArsTechnica.com and the CPU tab on the main AT site

 

[Gamingphreek]

Ok the HyperTransport technology is an interface, or rather an interconnet that connects the processors to the on Die memory controller, the northbridge (i think it is HTT), and all the other devices on the Processor Die. As for clockspeeds:

Original Nforce4 Pro150 only supported a maximum of 600MB/S IIRC, whereas the actual full speed was 800MB/S, AMD with the introduction of the IIRC Winchester chips (might have been the Venice cores) upped the HTT speed to 1000MB/S, which is where it currently is right now.

The onboard memory controller is simply really. Normally the memory controller lies in the Northbridge and is up to the manf (Nvidia, ATI, Via) to control how it is designed. It is also normally connected by the FSB. However, with that interface there was high latency and the transfer speeds were limited to the FSB. So to alleviate some of these problems, AMD, with the introduction of the A64, moved that memory controller onto the actual CPU die. Therefore, it is now connected by the extremely high speed HTT Bus, which eliminates any bandwidth issues, as well as any latency issues.

The memory controller is on ALL chips that use the Socket 754,939, and 940 interface. However all are slightly different. On the 754 interface, i believe that they still run at 800MB/S, and are still limited to single channel (64bit operation). The 939, the newest interface has the best memory controller for our (avg consumer) purposes. They support full 1000MB/S transfers as well as Dual Channel (128bit) memory operation. The 940 interface is a server interface. The memory controller on these chips supports Dual Channel and i believe they have the 1000MB/s but require registered DRAM for added stability (Because you are working in a server environment).

The northbridge isn't completely removed, as you still have your PCI-E controllers, your Onboard Audio, any SATA(2) or IDE interfaces. Essentially all your I/O with the excpetion of the memory controller is still on the Northbridge.

If you have any other questions feel free to ask. From what i hear, a lot of A+ teachers, know only the very basic

-Kevin