Can we extract CPU serial number from the CPU?

[Rudy Toody]

I'm letting my queue go empty so I can remove my heatsink to find my serial number for the RMA.
"But, wait," I thought. "What if it is buried in the CPU?"
Does anyone know?

 

[Orange Kid]

I believe that feature was removed a while back due to privacy concerns. Seem to remember some sort of "Intel is spying on us ballyhoo" and that went away after the Pentium series. I don't think any of the new stuff has that ability anymore. At least not enabled.

 

[biodoc]

The serial # for my 2700x is on the box. You'll need a magnifying glass or cell phone camera to read it though.

 

[shortylickens]

check the box. unless its OEM. then good luck.

 

[biodoc]

cat /proc/cpuinfo or lscpu did not give me a serial number. It did list the "bugs" though.

processor : 0
vendor_id : AuthenticAMD
cpu family : 23
model : 8
model name : AMD Ryzen 7 2700X Eight-Core Processor
stepping : 2
microcode : 0x8008206
cpu MHz : 3791.911
cache size : 512 KB
physical id : 0
siblings : 16
core id : 0
cpu cores : 8
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 13
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx hw_pstate sme ssbd sev ibpb vmmcall fsgsbase bmi1 avx2 smep bmi2 rdseed adx smap clflushopt sha_ni xsaveopt xsavec xgetbv1 xsaves clzero irperf xsaveerptr arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif overflow_recov succor smca
bugs : sysret_ss_attrs null_seg spectre_v1 spectre_v2 spec_store_bypass
bogomips : 7389.01
TLB size : 2560 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 43 bits physical, 48 bits virtual
power management: ts ttp tm hwpstate eff_freq_ro [13] [14]