Can someone explain memory strapping to me?

[supastar1568]

Hey folks,

Currently running an e8400 at 3.8Ghz with PC-8500 ram. I am running the FSB at 423 with an 9x multi. Obviously, wanting to get my ram as close to 1066 Mhz as possible. I have passed memtest, and multiple passes of prime, so I'm good, just want to confirm my memory setting.

I have the memory divider set to 2.50A, which is the 266Mhz strapping. This seems like my best bet, as it gets me to 1057 Mhz. Other options include 2.00A, 2.50A, 2.40B, 2.66D, etc.

Whats with the letters? Do they really mean anything if my fsb does not match the standard:

x.xxA -> 266MHz
x.xxB -> 333MHz
x.xxC -> 200MHz
x.xxD -> 400MHz

My FSB is at 423, which of course matches none of the above. 2.50A has worked for me although I am curious to understand how the strapping works with a different FSB set.

Thanks for the knowledge.

 

[supremelaw]

I too would like to know more about strapping.

Here's what I see in your settings:

423 MHz Bus Speed x 4 = 1692 MHz Rated FSB (using CPU-Z nomenclature)

423 x 9 Multiplier = 3.80 GHz Core Speed

423 x 2.5 = 1057 MHz = DDR2-1057 (effective)

1057 MHz / 2 = 528 DRAM bus clock (~= DDR2-1066 / PC2-8500)

If you preferred an FSBRAM ratio of 1:1 (which some do),
you would need to lower your DRAM bus clock to 423 MHz,
which will cause your DRAM to run a tad slower.

But, the difference might be so minimal, you probably
wouldn't notice it: chiefly because the Front Side Bus
is still running at the same speed -- to service the CPU.

As long as your system is stable at 423:528 (4:5)
you appear to have reached your "sweet spot."


I believe that strapping has to do with certain
FSBRAM ratios that a BIOS and chipset will permit
for any given overclock setting.

Anand has already written several reviews
in which strapping became an important factor
during certain overclocking experiments.

Use Google to limit your search as follows:

site:www.anandtech.com +strap +Anand


I hope this helps.

Sincerely yours,
/s/ Paul Andrew Mitchell, Inventor and
Webmaster, Supreme Law Library

All Rights Reserved without Prejudice


Link removed, check your PM box.
-Schadenfroh (AT Mod)

 

[supremelaw]

The Basics of Strap Selections, Dividers and Derived Memory Speeds

http://www.anandtech.com/mb/showdoc.aspx?i=3208&p=4


Sincerely yours,
/s/ Paul Andrew Mitchell, Inventor and
Webmaster, Supreme Law Library

All Rights Reserved without Prejudice


Link removed, check your PM box.
-Schadenfroh (AT Mod)

 

[supastar1568]

great reply thanks.

I have been searching for a while and have been very curious about this. My last AMD builds never had this sort of feature.

 

[n7]

You've already been linked to good info.

Different straps will correspond to different ratios.

Generally, lower straps will results in better latency/RAM performance, but can also be harder or impossible to stably run.

Since pure speed + bandwidth tends to always win with Intel, even though the higher straps are theoretically worse performance, you will generally reach the best memory clocks from those, & win in overall performance.

It's best to benchmark for yourself to see with one does the best

I don't know what mobo you have, but if you want to improve performance, look into tightening tRD; that boosts memory performance more than pretty much all but the first three primary timings.

 

[supastar1568]

Cool, looks like I am in a great position. I am using a 2.50A multi for my memory.

The "A" denotes a 200 strap, which is a default Trd of 6, which seems to be the best option. This also allows my memory to run at 1057 (with the 423 FSB), which is as close to stock speeds as I can get (~1066). I am memtest stable for 12 hours, prime95 blend for 20 hours, and small fft blend for 24 hours.

 

[supremelaw]

> I am memtest stable for 12 hours, prime95 blend for 20 hours, and small fft blend for 24 hours.

Sounds TOTALLY STABLE to me, especially considering how much computing
your machine did during those 3 periods to time!

Congratulations!!


Sincerely yours,
/s/ Paul Andrew Mitchell, Inventor and
Webmaster, Supreme Law Library

All Rights Reserved without Prejudice

 

[supremelaw]

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Thanks, all!


Sincerely yours,
/s/ Paul Andrew Mitchell, Inventor and
Webmaster, Supreme Law Library

All Rights Reserved without Prejudice