Can a Jaguar/Puma core access the whole L2 cache?

[Chicken76]

Looking at dualcores such as the 2650 Sempron, they all have 1MB of L2 cache. So the question arises: is it a modular (not à la Bulldozer) design, in which there's 1MB of cache for a pair of cores? If one of the cores is faulty, do they have to disable the whole "module" eliminating it's cache too?

 

[Enigmoid]

The entire L2 cache can be accessed by one core.

 

[Chicken76]

The entire L2 cache can be accessed by one core.

Thanks.