Calling all VHDL guru's

[tatteredpotato]

So I have this assignment for class to make a slot machine, so I figure the first thing I'll do is make a entity that outputs the random number i need. I've come up with the following:



LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.math_real.all; -- for UNIFORM, TRUNC
use ieee.numeric_std.all; -- for TO_UNSIGNED

entity rnd is
PORT
(
getRND : IN STD_LOGIC;
stim : OUT STD_LOGIC_VECTOR(11 downto 0)
);
end rnd;

ARCHITECTURE behavior OF rnd IS
BEGIN
process(getRND)
variable seed1, seed2 : positive; -- Seed values for random generator
variable rand : real; -- Random real-number value in range 0 to 1.0
variable int_rand : integer; -- Random integer value in range 0..4095
begin
-- Only give a new random on rising edge of the signal.
if getRND = '1' then
-- Initialize the seed variables...
-- These determine the starting value of the random function. Ideally they would change every time,
-- however that may not be possible in a basic digital system.
seed1 := 42;
seed2 := 893;
rand := 0.0;

-- Seeds using seed1 and seed2, returns a number between 0 and 1 in the rand variable.
UNIFORM(seed1, seed2, rand);

-- Converts the real to an integer between 0 and 4096 (12 bits).
int_rand := INTEGER(TRUNC(rand*4096.0));

-- Puts the value in a std_logic_vector.
stim <= std_logic_vector(to_unsigned(int_rand, 12));
end if;
end process;
end behavior;





Using Quartus 2 (7.1 Web Edition) I can make a symbol file just fine, however when I attempt a compilation, I get the following error:

Error (10414): VHDL Unsupported Feature error at rnd.vhd(18): cannot synthesize non-constant real objects or values

I've read that real types have to be constant or generic, the bad thing is I have no idea what that means. We didn't even go over variables or data types of any kind in class, so I don't even know what that means. From my C++ experience it makes me think that it means that the rand variable cannot be changed?

Also sorry if the code looks jumbled, it should show up fine on a decent width monitor.

 

[degibson]

The entire 'real' type exists only to make VHDL useful as a simulation language -- you cannot synthesize hardware that uses it. As a corollary, you cannot use UNIFORM() in hardware definitions -- only in testbenches.

Try googling 'LFSR' for an example of a hardware P-RNG.

 

[tatteredpotato]

When using the process statement, my professor has been doing something like this:

PROCESS(clk)
BEGIN
IF clk = '1' AND clk'EVENT THEN
--do some stuff.
END IF;
END PROCESS


I was under the impression that the "clk'EVENT" term was sort of implied by the process statement, so it's unnecessary. From my understanding the way process worked is that it gets run when any of the signals in the parentheses changes.