Calling all VHDL experts

[OOBradm]

Im looking to implement a 3 input NAND gate in VHDL for a hw assignment, but ive ran into the following problem:

say i have a line of code such as:

X1 <= a nand b nand c;

that actually becomes:
a nand b = x
x nand c = X1

instead I want it to become
X1 = nand( a,b,c)


any clue how to code this?

 

[jmcoreymv]

Try not(a and b and c)

 

[OOBradm]

Originally posted by: jmcoreymv
Try not(a and b and c)

were restricted to using 2+3 input NANDs, 2+3 input NORS, and 2 input XORS


but the thing is we cannot find a way to directly implement 3 input gates....

 

[jmcoreymv]

Are you trying to implement code that is synthesizable on an FPGA/CPLD? IIRC, Xilinx just uses 4-input lookup tables anyway and doesn't use actual gates.

 

[nd]

Seems like a silly assignment. Just because you did "A and B" in your VHDL doesn't mean it will synthesize to a 2-input gate.
Anyway, I think they're looking for something like this:

entity Nand3 is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
O : out std_logic
);
end Nand3;

architecture rtl of Nand3 is
signal X : std_logic;
begin
X <= A and B;
O <= not (X and C);
end rtl;

Then, you could just do X1 <= Nand3(A, B, C). And it uses the silly 'intermediate' signal like it sounds like the professor wants.