- Feb 13, 2011
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So, the PCI-E lane count on the chipset is being bumped to 24 from 20. I'm not quite sure how this is useful, however.
Let's say someone has a Z170 board where all 20 chipset-based lanes are in use and four of those are being used for an extremely fast NVMe SSD. The owner of the board decides he wants another NVMe SSD in the M.2 form factor, so he purchases one with Z270 motherboard and puts them in RAID 0.
This is the part that loses me - the connection between the chipset and CPU has the bandwidth of PCI-E x4, so throwing those NVMe drives into a RAID 0 should presumably do nothing due to being bottlenecked by the CPU-chipset bandwidth.
What am I missing?
Let's say someone has a Z170 board where all 20 chipset-based lanes are in use and four of those are being used for an extremely fast NVMe SSD. The owner of the board decides he wants another NVMe SSD in the M.2 form factor, so he purchases one with Z270 motherboard and puts them in RAID 0.
This is the part that loses me - the connection between the chipset and CPU has the bandwidth of PCI-E x4, so throwing those NVMe drives into a RAID 0 should presumably do nothing due to being bottlenecked by the CPU-chipset bandwidth.
What am I missing?