Sorry if inappropriate
- AMD said pipeline balancing in RDNA2, does this involve reduction of latency via reorganization of the VGPRs and scalar registers, and wave size (16 <- 20) or the wavefronts across SIMDs?
- Earlier reports indicated that the shaders would traverse the BVH and the traversals stored in texture cache. How is that the case with a Ray Accelerating Unit?
- How would the infinity cache be differently structured to traditional L3 CPU Cache?
- Bandwidth management beginning with RDNA1 shared L1 cache and the LLC, infinity fabric, indicate a future chiplet approach. How would they manage conflicting GPU processing (triangles?) without a hit on latency or power?