BD L3 cache OCing

[Anarchist420]

I don't have one and don't plan to get one, but I've never understood why the L3 cache is clocked so slow. Is it possible that the next chip revision will have L3 cache that could be safely OC'd to 2.8-3GHz? How much of a boost in performance would that give?

Is faster L3 cache likely to be important to AMD?

 

[Zap]

I've never understood why the L3 cache is clocked so slow.

Best guesses:

1) AMD was unable to get L3 to clock higher (reliably for all chips).

2) AMD found out that higher L3 clocks did not help performance enough.

3) AMD found out that higher L3 clocks increased the power envelope too much.

4) Combination of above.

 

[sm625]

There is some interesting discussion on the semiaccurate article page about Trinity's die. It seems the complexity of the cache is quadrupled for 4 modules vs two in terms of interconnects. So it is possible that a native 2 module trinity may have significantly improved L3 cache performance. If so then it proves there is much room for improvement on the 4 module version.

 

[ikachu]

There is some interesting discussion on the semiaccurate article page about Trinity's die. It seems the complexity of the cache is quadrupled for 4 modules vs two in terms of interconnects. So it is possible that a native 2 module trinity may have significantly improved L3 cache performance. If so then it proves there is much room for improvement on the 4 module version.

From what I know Trinity doesn't have L3 cache...

 

[Maximilian]

I was reading this bulldozer analysis yesterday:

http://www.extremetech.com/computing/100583-analyzing-bulldozers-scaling-single-thread-performance/3

Says something about higher L3 cache latencies were supposed to allow for higher clockspeeds.

 

[denev2004]

I can't understand why AMD keep L3 at NB-clock instead of core-clock either

 

[frostedflakes]

BD doesn't seem to benefit much from speeds >2.2GHz, might be the reason they didn't bother clocking it higher.

http://www.overclock.net/t/1140459/...nce-scaling-charts-max-ocs-ln2-results-coming

 

[AtenRa]

I believe BDs L2 is too large and 99% of desktop software doesn't even touch BDs L3, so no matter how fast it is, desktop software will not see any performance increase unless the software specifically calls the L3.

Edit: BD could get a nice performance boost (for desktop use) from higher clocks, faster L2 and removing the L3, reminds you something ?? (Trinity)

 

[brybir]

Cache frequency is usually directly related to the latencies that they can achieve. Some programs benefit from increased frequencies and others benefit from lower latencies.

The decision is also very dependent on the various algorithims that are used to populate the L2 and L3 cache.

For example, Intel optimization guidelines for the old P4s states that if there is little or no parallelism in the code due to instruction dependencies (instructions need results produced by previous instructions), high cache latencies can worsen the problem. In contrast, if the code is highly parrallel without significant dependencies, high cache latencies cause little or no performance penalty.

So for the P4, Intel made the choice to significantly lower cache latencies relative to Pentium III, as [I am guessing] that they felt that this was the proper trade off to make for that architecture. But, as shown in the link below, whether a CPU cache is "good" is as much dependent on the coding of the software as it is on the hardware engineers making the chip. This is one of the fundamental reasons why the same code can and does perform differently on different CPUs.

This is always a situational decision though and cache is a really complex beast. For example, the factors that determine latencies and throughput come from design, logic used to populate the cache, sensativity of the architecture to cache misses, manufacturing problems etc....so the engineers have to try to factor all of these things in when making design decisions.


Intel's website is really a treasure trove of technical information, even if some of it is pretty old by now:

http://software.intel.com/en-us/art...mr-4-processor-vs-the-pentiumr-iii-processor/

 

[denev2004]

I believe BDs L2 is too large and 99% of desktop software doesn't even touch BDs L3, so no matter how fast it is, desktop software will not see any performance increase unless the software specifically calls the L3.

Edit: BD could get a nice performance boost (for desktop use) from higher clocks, faster L2 and removing the L3, reminds you something ?? (Trinity)

I don't think so. At least its L3 is faster than Memory, which is never too large.
But I agree the large L2 seems strange...Anyway, I still blame the bad cache performance to the uncore structure.

 

[brybir]

I believe BDs L2 is too large and 99% of desktop software doesn't even touch BDs L3, so no matter how fast it is, desktop software will not see any performance increase unless the software specifically calls the L3.

Edit: BD could get a nice performance boost (for desktop use) from higher clocks, faster L2 and removing the L3, reminds you something ?? (Trinity)

It is possible, but cache population is usually more of a function of the CPU logic that decides what to put in the cache. That is to say that the coders can find ways to optimise code for a particular cache architecture, but they do not have that level of control to bypass a cache level. However, you could be correct if the cache size is incorrect relative to the instructions that could populate it such that BD is able to fit most of the useful stuff in L2, but I don't think that is the case with BD, as the cache size is pretty comparable to Intel's offerings and the trend is for larger L3 caches, not smaller.