Basic circuit theory

[atomheart]

I was given an equation to draw a circuit

"X Y Z (X + Y + Z) + ~X ~Y ~Z (X + Y + Z) + (~X + ~Y + ~Z) ~Z + X Z (Y + ~Z)=F"

My initial design used 22 gates but I was told you could get creative and reduce the amount of gates. After enough tinkering I got it down to 2 NAND gates.

The resulting equation from the 2 gate design is
"~(Z ~(X Y))=F"

The output from each circuit (results in truth table) is the same for both designs even though the equation and amount of gates is different. My question is, will both these designs essentially function the same? Or did I reduce it too much and change the core of its function?

 

[TuxDave]

I assume your logic conversion is right. So in steady state, meaning after the output has finally propagated through all the logic, you will be identical. What you get in the physical domain is a better transient response (your output will settle to the right output faster) and smaller area/power in circuits. "Functionality" always refers to logical behavior so you are functionally the same. However you will have a different timing behavior which could be good (max path) or bad (min path)

 

[atomheart]

I assume your logic conversion is right. So in steady state, meaning after the output has finally propagated through all the logic, you will be identical. What you get in the physical domain is a better transient response (your output will settle to the right output faster) and smaller area/power in circuits. "Functionality" always refers to logical behavior so you are functionally the same. However you will have a different timing behavior which could be good (max path) or bad (min path)

That helps, thanks. Would you say all that matters is input and output? When talking in terms of the circuit's function. I was told having more gates introduced more latency, what would be a negative to having a lower timing?

 

[lakedude]

Oooh can I play?

I get z'+xy but it has been a while, could have made a mistake.

Here is how I does it:

The first term xyz(x+y+z) simplifies to xyz, already got all 3 inputs from the "and" part so the "or" part is not needed.

The second term x'y'z'(x+y+z) is zero, can't have an input and the opposite at the same time.

Skipping the third term, the last term xz(y+z') becomes xyz + xzz'. xyz is redundant with the first term so we can toss it and xzz' is zero cause you can't have both z and z' at the same time so the entire last term can be tossed out.

I only got the third term from z'(x'+y'+z') to x'z' +y'z'+z' for a final equation using Boolean algebra of:

xyz+x'z'+y'z'+z'

But wait that was not my final answer! I makes a truth table 10101011 and plugs that into a Karnaugh Map which gives 1s @ all 4 corners plus a stray 1 @ xyz

The 4 corners make for z' and I combined the xyz entry with xyz' to yield xy.

Final answer z'+xy!

Is that right?

 

[lakedude]

Oops now I see how I could have used absorption to make the 3rd term just z'...

Then I would have had xyz+z' before using the K-map.

 

[TuxDave]

That helps, thanks. Would you say all that matters is input and output? When talking in terms of the circuit's function. I was told having more gates introduced more latency, what would be a negative to having a lower timing?

Yeah, most of the time all that matters is input and output logic. Once you get into implementation, the more gates you use, the longer it may take for the correct value to appear at the output. 99% of the time faster is always better. However there is a concept of "min paths" which relates to how data travels between two sequential/timing elements.

The classic example is the washer-dryer example. Ideally when both open, dry clothes go out, wet clothes from the washer go to the dryer, dirty clothes go into the washer. And then they both close and do their business. A min path would be if the dirty clothes basically go so fast that it passes through the washer and directly to the dryer. But this is usually solvable by slowing it down but the best way to slow it down is NOT to use a large # of gates, but to use the minimum number of gates and just add small devices at the end to buffer it along.

 

[PandaBear]

In steady state they would be identical and encouraged. In analog / RF types of application the transient behavior could be different and you will likely have different possible path before reaching steady. It is not just going from point A to point B on a K map, but in a circuit with a lot of gates you may see going back and forth between different points before reaching steady. The fewer gates you have, the less bouncing around you will see.

 

[Ichinisan]

Is it possible to learn this kind of stuff on my own? ...or is formal training pretty-much required?

 

[TuxDave]

Is it possible to learn this kind of stuff on my own? ...or is formal training pretty-much required?

Getting the basics of "what does AND mean, what does OR mean, what does NOT mean" is the first step. Then you start learning how to analyze complex statements, then you learn how to simplify and optimize. This is all still purely logic without any notion of implementation or application. Up to this point, it's very doable.

Application is sort of like learning how to program. You can learn about binary math and various logic structures. I find this step also pretty easy. Once you understand how binary math works, you can apply the logic equations and everything you learned in step 1.

Implementation, beyond the "an AND gate is some magic black box" requires some amount of formal training if you really want to understand good and bad implementations. This one is probably a bigger hurdle for most.

 

[harrkev]

The BEST way to learn is to help design a multi-million gate ASIC.

Back when I used to do FPGA work for a living I understood setup paths very well, but FPGAs never have hold problems. Now I do ASIC work (both front end and back end), and I have found that hold problems are often harder to understand and fix than setup problems.

The tools are supposed to fix timing problems by themselves, and hold problems SHOULD be easy to fix (just add delay cells). When you still have hold issues, you have to figure out why the stupid tool war not able to fix it. Very frustrating for tool that cost more to license than my first house cost to buy.

 

[TuxDave]

The BEST way to learn is to help design a multi-million gate ASIC.

Back when I used to do FPGA work for a living I understood setup paths very well, but FPGAs never have hold problems. Now I do ASIC work (both front end and back end), and I have found that hold problems are often harder to understand and fix than setup problems.

The tools are supposed to fix timing problems by themselves, and hold problems SHOULD be easy to fix (just add delay cells). When you still have hold issues, you have to figure out why the stupid tool war not able to fix it. Very frustrating for tool that cost more to license than my first house cost to buy.

Wait until you get hold and setup violations on the same start and end point while going through the same gates too. That's actually one of my interview questions. Haha. (and it's not a theoretical textbook case too. I happened to design such a mess and found it interesting when I saw it)

 

[harrkev]

Wait until you get hold and setup violations on the same start and end point while going through the same gates too. That's actually one of my interview questions. Haha. (and it's not a theoretical textbook case too. I happened to design such a mess and found it interesting when I saw it)

I know. I have seen that too - a few times. Very frustrating... Trying to figure out what is going on is quite frustrating.

What is worse is finding hold violations, and there is NO REASON for it. All paths to a regsiter have plenty of setup slack, but there are hold problems. Then, you add several delays by hand (pain in the rear), and everything passes. Why couln't Encounter do that???

**EDIT**
Ok. I just re-read your post. The same path was causing a setup and hold violation at the same time? How does that happen? I have seen register inputs with setup and hold violations, but the paths were different.

BTW: Where do you work?

 

[TuxDave]

I know. I have seen that too - a few times. Very frustrating... Trying to figure out what is going on is quite frustrating.

What is worse is finding hold violations, and there is NO REASON for it. All paths to a regsiter have plenty of setup slack, but there are hold problems. Then, you add several delays by hand (pain in the rear), and everything passes. Why couln't Encounter do that???

**EDIT**
Ok. I just re-read your post. The same path was causing a setup and hold violation at the same time? How does that happen? I have seen register inputs with setup and hold violations, but the paths were different.

BTW: Where do you work?

Intel.

This was on a phase path between a phase 2 latch and a phase 1 clock enable. Min is falling edge of clock on latch to falling edge of clock on clock cell. Max is falling edge of clock on latch to rising edge of clock on clock cell. The timing window is really small and it was made impossible by a very long unshielded RC segment (causing the wire delay to dominate the path and be SUPER slow on max and SUPER fast on min).

 

[harrkev]

I try to avoid latches whenever possible.

On my current project, we have a rule: the clock scheme must fit on one letter-size paper drawn with a dull crayon.

I work at Agilent.

 

[ricardo80]

@atomheart: I think your logic is right whether you have reduced the number of gates from 22 to 2 because in digital you can make the circuit by different types and number of gates and your logic will remain the same and if you want to check the accuracy of the logic, put the same values of X, Y, Z in both the equations and if the answer is same then it means your logic is same.

pcb manufacturing

 

[aigomorla]

BTW: Where do you work?

Intel.

i thought that was a epic reply.. lolol...

i didnt know u worked at intel dave...

 

[atomheart]

Funny to see this old thread pop up, thanks for the help from all who contributed.

That assignment was from the "introduction to engineering" course I took last year, apparently the professor only gave us that assignment to screw with us.

In January 2014 I will be starting the formal course on digital logic, I'll surely have more questions then.

 

[dmens]

Intel.

This was on a phase path between a phase 2 latch and a phase 1 clock enable. Min is falling edge of clock on latch to falling edge of clock on clock cell. Max is falling edge of clock on latch to rising edge of clock on clock cell. The timing window is really small and it was made impossible by a very long unshielded RC segment (causing the wire delay to dominate the path and be SUPER slow on max and SUPER fast on min).

Sounds familiar. I remember my domino array read feeding your logic creating a slow max pulldown and a fast min retain. I blame the architects fault because they insisted on no latch at the output in order to fit the pipeline.

Solution: stop routing stuff really far away out of a bare array read.