- Aug 21, 2005
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Hey guys,
I got a homework question in my "advanced" computer architecture class (2nd graduate level course in the series) this semester and I'm a little confused on one of the questions. It's not a question of theory, rather a question of implementation. Here is the question:
"The MIPS pipeline shown in Table 2.7 employs a two-phase clocking scheme that makes efficient use of a shared TLB, since instruction fetch accesses the TLB in phase one and data fetch accesses in phase two. However, when resolving a conditional branch, both the branch target address and the branch fall-through address need to be translated during phase one – in parallel with the branch condition check in phase one of the ALU stage – to enable instruction fetch from either the target or the fall-through during phase two. This seems to imply a dual-ported TLB. Suggest and architected solution to this problem that avoids dual-porting the TLB."
This question suggests that the ALU needs to both compute the branch addresses (taken address and not taken address) along with doing the branch check validation (taken and not taken). We are supposed to avoid dual-porting TLB's, but I can't think of how one could use one TLB and solve both checks. I'm thinking maybe data-forwarding in the ALU stage (the table is a 5 stage pipeline, where each stage has two phases) might solve the problem, but I'm under the impression that maybe that would only work for a branch fall-through, and not a branch taken.
Thoughts?
I got a homework question in my "advanced" computer architecture class (2nd graduate level course in the series) this semester and I'm a little confused on one of the questions. It's not a question of theory, rather a question of implementation. Here is the question:
"The MIPS pipeline shown in Table 2.7 employs a two-phase clocking scheme that makes efficient use of a shared TLB, since instruction fetch accesses the TLB in phase one and data fetch accesses in phase two. However, when resolving a conditional branch, both the branch target address and the branch fall-through address need to be translated during phase one – in parallel with the branch condition check in phase one of the ALU stage – to enable instruction fetch from either the target or the fall-through during phase two. This seems to imply a dual-ported TLB. Suggest and architected solution to this problem that avoids dual-porting the TLB."
This question suggests that the ALU needs to both compute the branch addresses (taken address and not taken address) along with doing the branch check validation (taken and not taken). We are supposed to avoid dual-porting TLB's, but I can't think of how one could use one TLB and solve both checks. I'm thinking maybe data-forwarding in the ALU stage (the table is a 5 stage pipeline, where each stage has two phases) might solve the problem, but I'm under the impression that maybe that would only work for a branch fall-through, and not a branch taken.
Thoughts?