[AviationWeek] Moore's Law No More

[witeken]

The next 10 years will be extremely interesting in any case with EUV, 450mm, post-silicon, post-CMOS, quantum computing, maybe IBM's brain-like chip takes off, exascale, further integration of the dGPU in the CPU, photonics, x86 in phones.

 

[TuxDave]

Oh look, more pundits declaring Moores Law dead. Back to 1992 we go.

Heh, hearing this sort of reminds me of the a person's ability to predict when a red light is about to turn green.

"okaaay.... NOW...... NOW. NOW......... NOW, NOW, NOW......"
<light turns green> "NOW"

"I'm a genius"

 

[aigomorla]

Cool! No, really, you need really good cooling for this to work. LN2 cooling good. Literally.

or u need a high temperature super conductor.

 

[CrazyElf]

For them it is all the harder to sell management and shareholders on a 10yr timeline for the ROI to tip positive.

Having lived and worked through many wafer size transitions and litho transitions, when I see the degree of hesitation and delay to which 450mm and EUV are both experiencing from the economics side of the equation (R&D vs. estimated demand and projected amortization) I cannot make any compelling argument that we will ever manage to step across the next economic chasm to 600mm and BEUV (Beyond EUV, yes it is a real thing).

This may sound like a strange question, but how big could a wafer get realistically?

200 mm > 300 mm > trying to get to 450 mm > 600 mm?

A lot of companies are hesitant to go to 450mm as is. Will we even get to 600mm?

So it would seem the economic limit will be reached before the technical?

 

[jpiniero]

I don't think you will see anyone other than Intel attempt 450 mm until (if?) EUV shows up.

 

[witeken]

I don't have any technical knowledge about this, but I don't see why it wouldn't be possible. But the thing is that it is a huge investment. 300mm was $20B or so. I don't think this is something 1 company can do. So if only Intel would see benefit from 600mm, that won't be enough. 450mm will give a ~40% cost advantage, so any company who wants to stay at the leading edge, will have to move to 450mm as well, so that will bring some consolidation. But since fabs are already multiple billion dollars, I don't think we will see any plans for 600mm in the near future.

 

[SAAA]

The benefits that derived from a shrink in the past allowed to reduce the cost vs the previous node and as a side plus to increase performance of all integrated circuits.
It's clear as crystal that the day those price reductions go away it will be only due to competition if any fab choses to develop a smaller and pricier product.
But at a certain point physical limits will prevent even that, using current or similar tech of course, so either we will find something else or computational power will stall.
By that time Moore's Law will be dead by long tough, because it's definition talks about transistors and price, not positron brains or the likes...

 

[Idontcare]

This may sound like a strange question, but how big could a wafer get realistically?

200 mm > 300 mm > trying to get to 450 mm > 600 mm?

A lot of companies are hesitant to go to 450mm as is. Will we even get to 600mm?

So it would seem the economic limit will be reached before the technical?

I don't have any technical knowledge about this, but I don't see why it wouldn't be possible. But the thing is that it is a huge investment. 300mm was $20B or so. I don't think this is something 1 company can do. So if only Intel would see benefit from 600mm, that won't be enough. 450mm will give a ~40% cost advantage, so any company who wants to stay at the leading edge, will have to move to 450mm as well, so that will bring some consolidation. But since fabs are already multiple billion dollars, I don't think we will see any plans for 600mm in the near future.

There is no technical limit on wafer size.* Really, you could make a silicon wafer the size of the moon (or bigger) if you had the necessary resources.

This is to be contrasted with scaling (shrinking) where you truly do have physical limits on how small atoms and sub-atomic particles (electrons/holes) are.

The limitations on wafer size are purely economic, always have been. And it isn't the economics of the wafer itself that is the problem, it is the equipment (the tools in the fab that process the wafers).

My memory will be a little off here because it was long time ago but I recall seeing 450mm wafers "blanks" back in the 90's in tool suppliers R&D labs. The silicon wafer people could make the wafers, just as they can make 600mm and 900mm silicon ingots now, but it is another thing to build the >$10m tools necessary to take those wafers and do something with them.

Intel might be the first to have a 450mm fab, but I expect one of the memory companies (Micron/Samsung/Hynix/Toshiba/etc) to be the first to have HVM 450mm fabs given the inherent product volumes and cost sensitivities that come with their ICs.

But 600mm? Good luck getting the entire tool supply eco-system to pony up the R&D money necessary to outfit a 600mm pilot line in a fab somewhere. Those tools will have a 10+ year development timeline and nowadays there isn't a shareholder or a board of director to be found that has the desire to get into that game.

If 600mm happens it will be because the fab owners jointly agree to fund an industry-wide tool development consortia, basically paying the R&D in advance instead of paying afterwards in terms of amortized expenses built into the tool price 10 years later. (not too unlike what ASML did, but it would need to be generalized across all tool suppliers and not be locked into a specific tool supplier)

* obviously if you made the wafer too big then it would collapse under the pressure of its own field of gravity, so technically there is an upper-limit as well, but that is kinda pedantic

 

[Xpage]

I would think the main issue with getting to big was that the thickness of the wafer would need to increase to support it along with the fact a larger wafer remains any variation in in movement become greater as the diameter increases when that wafer is spinning.

Think why HDDs are not 5.25" anymore or larger, they would hold much more data but the size to hold that data bit has gotten smaller and probably out of the economically feasible range of producing something to write the data bit (or ethch that transistor) within the parameters

 

[Idontcare]

I would think the main issue with getting to big was that the thickness of the wafer would need to increase to support it along with the fact a larger wafer remains any variation in in movement become greater as the diameter increases when that wafer is spinning.

Think why HDDs are not 5.25" anymore or larger, they would hold much more data but the size to hold that data bit has gotten smaller and probably out of the economically feasible range of producing something to write the data bit (or ethch that transistor) within the parameters

Nah, wafer thickness isn't a limiting issue, not even an economic one. But what you speak to in regards to within-wafer process uniformity and angular momentum effects during processing are part and parcel to why the tools needed to process larger and larger wafers take more time to develop and cost all the more to manufacture.

In the history of wafer size transitions, it has always been the tool development cost, not the cost of developing and producing larger wafers, that has gated the rate of change over the years.

And what we are witnessing with 450mm tool development is that it is nigh impossible for this industry to get to 600mm with its current business model. Not unless the fab companies become tool manufacturers again like we were in the 70's and 80's.

 

[witeken]

There is no technical limit on wafer size.* Really, you could make a silicon wafer the size of the moon (or bigger) if you had the necessary resources.

This is to be contrasted with scaling (shrinking) where you truly do have physical limits on how small atoms and sub-atomic particles (electrons/holes) are.

The limitations on wafer size are purely economic, always have been. And it isn't the economics of the wafer itself that is the problem, it is the equipment (the tools in the fab that process the wafers).

My memory will be a little off here because it was long time ago but I recall seeing 450mm wafers "blanks" back in the 90's in tool suppliers R&D labs. The silicon wafer people could make the wafers, just as they can make 600mm and 900mm silicon ingots now, but it is another thing to build the >$10m tools necessary to take those wafers and do something with them.

Intel might be the first to have a 450mm fab, but I expect one of the memory companies (Micron/Samsung/Hynix/Toshiba/etc) to be the first to have HVM 450mm fabs given the inherent product volumes and cost sensitivities that come with their ICs.

But 600mm? Good luck getting the entire tool supply eco-system to pony up the R&D money necessary to outfit a 600mm pilot line in a fab somewhere. Those tools will have a 10+ year development timeline and nowadays there isn't a shareholder or a board of director to be found that has the desire to get into that game.

If 600mm happens it will be because the fab owners jointly agree to fund an industry-wide tool development consortia, basically paying the R&D in advance instead of paying afterwards in terms of amortized expenses built into the tool price 10 years later. (not too unlike what ASML did, but it would need to be generalized across all tool suppliers and not be locked into a specific tool supplier)

* obviously if you made the wafer too big then it would collapse under the pressure of its own field of gravity, so technically there is an upper-limit as well, but that is kinda pedantic

This is about what I was thinking, but it isn't a free lunch in terms of technical challenges:

Wafer transitions offer one of the rare periods when new approaches can be developed and integrated into facilities plans. During the 300mm transition, significant developments occurred in factory automation and wafer handling. Similarly, the 450mm transition is a window to update the industry approach to a number of fab systems. Rising energy costs, water scarcity, and climate change will continue to present both challenges and opportunities for semiconductor manufacturing in the 450mm era. These sustainability concerns are driving demand for tools that can more reliably and cost-effectively achieve a shared vision of resource balance.

Other initial technical problems in the ramp up to 300 mm included vibrational effects, gravitational bending (sag), and problems with flatness. Among the new problems in the ramp up to 450 mm are that the crystal ingots will be 3 times heavier (total weight a metric ton) and take 2-4 times longer to cool, and the process time will be double. All told, the development of 450 mm wafers require significant engineering, time, and cost to overcome.

 

[firewolfsm]

IBM's SyNAPSE chip has already been fabbed at 28nm with 4.5B transistors and consumes only 0.7W running tasks at 1KHz that take hundreds or thousands of watts for traditional processors. Something so low power could also be stacked like DRAM on cell phones, which can already be stacked 16 layers high (this would also minimize axon (interconnect) length). This is more likely to be next major trend in processing as features really don't need to be smaller, we just need to use them more effectively.

 

[CrazyElf]

If 600mm happens it will be because the fab owners jointly agree to fund an industry-wide tool development consortia, basically paying the R&D in advance instead of paying afterwards in terms of amortized expenses built into the tool price 10 years later. (not too unlike what ASML did, but it would need to be generalized across all tool suppliers and not be locked into a specific tool supplier)

* obviously if you made the wafer too big then it would collapse under the pressure of its own field of gravity, so technically there is an upper-limit as well, but that is kinda pedantic

Real limit seems to be economic then.

Hmm, as wafers get larger in diameter, they will have to get thicker (to prevent them from breaking under their own mass). But yeah, tooling cost is the issue. I would expect than as wafers get bigger, they'd absorb a higher proportion of total costs as litho costs. I wonder what diameter than would be the lowest total cost? The capital investment is pretty big it would seem.

I mean, the other issue right now is that it is looking like ASML's EUV has hit problems so to speak. It appears to be delayed. Any idea of roll out times? I don't think it's happening in the next few years. Looking forward, even 14nm has proven problem plagued for Intel. What will the jump to 10nm be like? Will they have to use something crazy like "quadruple patterning", especially in light of the EUV issues.

I think that we may end up in a future where semiconductors end up as interesting as say, cars. There's incremental improvements here and there but the exponential era is gone.

 

[hal2kilo]

Its not just the fab owners and process developers who have to be sold on the long-term economic picture, the tool makers and chemical suppliers do as well.

Look at the current pace of 450mm development, or EUV for that matter. Everyone upstream of the fabs in terms of equipment and materials has to be making their R&D investments years ahead of the process development teams at leading edge companies like Intel and Samsung.

For them it is all the harder to sell management and shareholders on a 10yr timeline for the ROI to tip positive.

Having lived and worked through many wafer size transitions and litho transitions, when I see the degree of hesitation and delay to which 450mm and EUV are both experiencing from the economics side of the equation (R&D vs. estimated demand and projected amortization) I cannot make any compelling argument that we will ever manage to step across the next economic chasm to 600mm and BEUV (Beyond EUV, yes it is a real thing).

Too bad Xray lithography didn't pan out. Made a killing in JMAR though, caught the right end of some pump and dump.

 

[Idontcare]

I think that we may end up in a future where semiconductors end up as interesting as say, cars. There's incremental improvements here and there but the exponential era is gone.

Pretty much. Going 3D doesn't solve the problem either, your cost only increase with 3D as you add more layers, there is no intrinsic cost-lowering per xtor mechanism in that manufacturing approach versus the present areal shrinkage mechanism.

And you can only double the layers so many times before you get to layer counts that make the mathematics simply untenable. 10 layers becomes 20, 40, 80, 160, 320, 640 and then...you are using entire wafers of stacked chips to produce a single 3D IC, or the wafer spends 3 years of cycle time in the fab simply to have enough days per layer of processing to exit the fab as a finalized 3D product.

None of that enables lower cost per xtor or per IC.

It will be a dreadfully slow incremental rate of improvements, and just like the auto industry there will be no flying car for us at the end of the century.

 

[witeken]

I mean, the other issue right now is that it is looking like ASML's EUV has hit problems so to speak. It appears to be delayed. Any idea of roll out times? I don't think it's happening in the next few years. Looking forward, even 14nm has proven problem plagued for Intel. What will the jump to 10nm be like? Will they have to use something crazy like "quadruple patterning", especially in light of the EUV issues.

EUV is working right now, the problem is that it needs to be good/fast enough for HVM. Mark Bohr said 10nm could be possible, but it might be too late, so it will be used at 7nm for sure. I don't even think there's any sensible alternative at that node.

 

[jpiniero]

IIRC, the earliest I had heard was 2018 for EUV.

 

[witeken]

ASML is now saying that their machines will be ready for HVM in 2016. They reached 637 wafers per day (34WPH) in the second quarter. They want 70WPH in 2014 and 125WPH in 2015.

 

[CrazyElf]

It will be a dreadfully slow incremental rate of improvements, and just like the auto industry there will be no flying car for us at the end of the century.

Semiconductors scaled better than pretty much anything else in history. It was a fascinating run.

I don't expect any other miracles. III-V materials like Indium Arsenide have been said to cost 5-10x as much per wafer vs silicon.

Graphene is decades away, as are others like vacuum tube transistors.

http://www.extremetech.com/extreme/...istor-that-could-one-day-replace-silicon-fets

Graphene acts as the gate, source, and drain, hexagonal boron nitride (h-BN) is the gate insulator, and molybdenite (molybdenum disulfide) is the channel.

http://www.extremetech.com/extreme/...istor-could-be-the-future-of-fast-electronics

Pretty cool stuff. But could it replace silicon?

 

[ShintaiDK]

Semiconductors scaled better than pretty much anything else in history. It was a fascinating run.

I don't expect any other miracles. III-V materials like Indium Arsenide have been said to cost 5-10x as much per wafer vs silicon.

Graphene is decades away, as are others like vacuum tube transistors.

http://www.extremetech.com/extreme/...istor-that-could-one-day-replace-silicon-fets

<quote>Graphene acts as the gate, source, and drain, hexagonal boron nitride (h-BN) is the gate insulator, and molybdenite (molybdenum disulfide) is the channel.</quote>

http://www.extremetech.com/extreme/...istor-could-be-the-future-of-fast-electronics

Pretty cool stuff. But could it replace silicon?

Its still based on silicon as your picture shows with the backgate and dielectric.

 

[Idontcare]

Semiconductors scaled better than pretty much anything else in history. It was a fascinating run.

I don't expect any other miracles. III-V materials like Indium Arsenide have been said to cost 5-10x as much per wafer vs silicon.

Graphene is decades away, as are others like vacuum tube transistors.

http://www.extremetech.com/extreme/...istor-that-could-one-day-replace-silicon-fets

http://www.extremetech.com/extreme/...istor-could-be-the-future-of-fast-electronics

Pretty cool stuff. But could it replace silicon?

What you are discussing is related to electrical performance, not areal scaling.

Performance, electrical parametrics, will continue to scale higher and higher for decades to come. Of that there is little to be concerned.

But it won't get any smaller, and that is where the key enabler of Moore's law (economics) dies out. Scaling and making things smaller so they were cheaper on a per xtor basis was the enabler for cost reduction.

Everything you see on the table now, be it 2.5D, 3D, stacking, material changes, etc, are all to improve performance but do very little to address cost reduction.

But we are another decade away from having no more shrinks, so no reason to get worried about it just yet.

 

[CrazyElf]

At this point, I'm open to anything that gives a decent performance increase. Ultimately, electrical performance might be able to give us some increases.

The only thing I have seen that gives areal scaling for a bit longer is FD SOI. Interesting article to read on this:
http://www.soitec.com/pdf/WP_handel-jones.pdf

ST Micro in particular seems to be pushing very aggressively for FD SOI and they claim that it might be able to give us 1-2 more nodes worth of scaling in terms of improving price per transistor.


Kind of off-topic, but I wonder, would a 20nm FD SOI behave more like planar in terms of scaling? Maybe respond a bit better to voltage when overclocking compared to the current FinFET implementation?