Attn: Wingznut, other Intel engineers - Question about dual-core P4 cache architecture...

[TerryMathews]

There was a decent little debate on the 2cpu forums, and I can't find any concrete information to go one way or the other.

Basically, how is the cache set up in these new dual-core P4s? I know it's 2MB, 1MB per processor. But do they each have an individual cache or are they both somehow concurrently accessing the same cache?

If they have seperate cache, what's the interconnect frequency? Core, bus, or something in-between?

 

[MrDudeMan]

i would imagine they cant tell you extremely specific information. i would be interested to know the answers, but im guessing some of them might be classified until release.

 

[Bassyhead]

The L1 and L2 caches are exclusive and each core has a separate interface to the front side bus.

http://www.extremetech.com/article2/0,1558,1771882,00.asp

 

[TerryMathews]

Originally posted by: Bassyhead
The L1 and L2 caches are exclusive and each core has a separate interface to the front side bus.

http://www.extremetech.com/article2/0,1558,1771882,00.asp

Yes, but that doesn't really answer my question. I'm operating under the assumption that the P4D is like two Xeons on one chip, and the cache data is interchanged via the northbridge, which is incredibly slow when you consider that there's no good reason for the cache data to hit the system bus. Doing the interchange on the processor would be at least 4x faster. And it's something that SMP systems do a lot.

This sounds like another case of "let's slap something together quick so we can beat AMD out the gate". Looks like we'll have to wait for the next-gen dual core P4 to get revolutionary performance.

 

[Bassyhead]

Originally posted by: TerryMathews

Originally posted by: Bassyhead
The L1 and L2 caches are exclusive and each core has a separate interface to the front side bus.

http://www.extremetech.com/article2/0,1558,1771882,00.asp

Yes, but that doesn't really answer my question. I'm operating under the assumption that the P4D is like two Xeons on one chip, and the cache data is interchanged via the northbridge, which is incredibly slow when you consider that there's no good reason for the cache data to hit the system bus. Doing the interchange on the processor would be at least 4x faster. And it's something that SMP systems do a lot.

This sounds like another case of "let's slap something together quick so we can beat AMD out the gate". Looks like we'll have to wait for the next-gen dual core P4 to get revolutionary performance.

I believe your assumption is correct, that a P4D is basically 2 CPUs on one die that each independently connect to a northbridge. Perhaps someone can clarify if Intel plans to somehow connect the caches together. I believe there were some SMP systems that did have connected caches. I think the Athlon MP had a bus that connected the L2 caches together, not sure.

 

[TerryMathews]

Originally posted by: Bassyhead
I believe your assumption is correct, that a P4D is basically 2 CPUs on one die that each independently connect to a northbridge. Perhaps someone can clarify if Intel plans to somehow connect the caches together. I believe there were some SMP systems that did have connected caches. I think the Athlon MP had a bus that connected the L2 caches together, not sure.

No, AXP/MPs had to interchange over the system bus - they were more efficient at it than even P4s because each AXP has an independent link to the northbridge - Xeons are still using the antequated shared bus architecture.

Taking cache coherency issues off the system bus will speed up cache reconciliation, and increase available bus bandwidth for non-cached data.

 

[kpb]

From arstechnica's latest post on the issue it does indeed seem like the caches are completely independant and any communication will have to occur over the normal FSB means. The pentium d is literally 2 prescot chips on 1 die. For all intensive purposes it's gonna be identical to a current dual processor system just with 1 socket. The ars article goes as far as to say they will cut out a pentium d and if one of the 2 cores won't work they will cut the non-working core off and sell it as a regular prescott.

 

[complacent]

Originally posted by: kpb
For all intensive purposes

Don't want to be nit-picky, but someone should tell you...
That is a malapropism. It is "for all intents and purposes", not intesive purposes.

 

[Peter]

The P4D, from its public presentations, is two completely separate P4 connected on the front side bus.