Possible yes, but if it is more logical then simply using SLI combined with tiling would be something else(no clue myself). It would seem to me that it would be easier to implement SLI utilizing tiling then STI, though it would be possible to greatly reduce the amount of duplicate texture reads required, bandwith in a multi chip tiling solution wouldn't be anywhere near as important as it is now. Consider the Kyro is swinging it out and besting in some cases a GF DDR with significantly less bandwith in bandwith limited situations, throw 5ns DDR on a chip as effecient as the Kyro with the power of the GF2U. You could be looking at ~4GTexels effective fillrate with a single chip.
Why would a company want to run multi chip though? Using multiple chips is less economical then designing one more powerful chip, not to mention you waste RAM with texture duplication and with an effective tiling implementation, memory bandwith becomes significantly less of a factor. Everyone loses with multi chip in terms of costs, manufacturer, consumer and investor.