ATI/TSMC using diagonal interconnects to increase performance

[Jeff7181]

Link

 

[Killrose]

"Cadence X Architecture design solutions for TSMC?s 0.13 micron and 0.11 micron process nodes are now available to select customers under Cadence?s value-based business model. X Architecture solutions for TSMC?s 90nm and 65nm process technologies are currently under development."

I wonder if this is why R520 is not quite ready due to the statement that the 90nm process is currently under development? Perhaps Ati is using the X Architecture with thier new chip?