Athlon cache subsystem questions

[Soulkeeper]

what kinda set-associativity do the L1 and L2 caches of the athlon have ??
I think i remember reading somewhere that the L2 is 8 way set associative if this is true is it also true for the L1 cache ??
are blocks still addressed in 64 byte chunks ?? as with the slot a athlons

 

[AndyHui]

Both the ThunderBird and Palomino (along with their Duron derivatives) feature 2-way associativity for both the L1 D and I caches.

The L2 cache has 16-way set associativity. The cache line size is 64 bytes.

 

[Soulkeeper]

thanks