Athlon 64 bus speeds, clock generators, HT links... huh?

[Jeff7181]

I'm trying to figure out how all this works. I know a crystal is used to generate a frequency, then that frequency is multiplied to get sort of a reference frequence by which all other things are multiplied by to get things like the frequency of the HT link, RAM speed, CPU core speed. I don't really know how to phrase my question...

I've been told the crystal is about a 14 Mhz crystal, and it's multiplied by 14 to get about 200 Mhz, which is the reference frequency. Then to get the speed of the HT link, is multiplied by 4 to get the 800 Mhz 16-bit HT link (or 3 in the nForce3 150's case to get 600 Mhz)... and multiplied by the CPU's multiplier to get 2000 or 2200 Mhz... then just the reference frequency is used for the RAM speed of 200 Mhz.

So... how fast is data transferred to and from the memory controller? Is it the speed of the HT link? And is it double pumped like the FSB of the Athlon XP?

 

[andreasl]

The memory controller and all HT ports are connected to each other through the Crossbar. Think of it as a hub. The datapath is 64-bit wide and runs at core speed (~2GHz). This gives it about 16GB/s bandwidth. This is the equivalent of a traditional FSB to a Northbridge chip. Except there is no FSB, just another datapath on the chip die.

K8 overview

 

[Jeff7181]

Hmmm... since we know the motherboards and CPU's are capable of higher FSB's, I guess it would be beneficial to use higher speed RAM, especially with the socket 754 boards since they don't have dual channel and all the memory bandwidth it can get will increase performance like it did with the 533 Mhz bus P4's since the RAM is now the limiting factor for the A64?

 

[andreasl]

Not even dual channel comes close to maximizing the bandwidth of the crossbar/memory controller datapath. 6.4GB/s is far away from 16GB/s. And the internal bandwidth scales up perfectly with core speed increases. In effect, the traditional FSB as a bottleneck in the system has been completely removed. This leaves the DRAMs themselves as the bottleneck. So for every increase in DRAM speed there will be a performance increase for code that access memory frequently (=all realworld code). Dual channel A64's will also recieve the same performance benefit from faster DRAMs.

You can call the HT link on the A64 an FSB but it really isn't one. It does not serve the same purpose as on a traditional CPU+Northbridge system. It no longer have to connect the CPU to the DRAM and I/O, only the I/O. Oh and AMD actually calls it PSB these days

 

[Jeff7181]

Wonder how long before DDRII is supported by Athlon-64 processors... probably a safe bet that it's at least 6 months away?