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Athlon 4/MP any better than Athlon at RC5?
- Thread starter xtreme2k
- Start date
BurntKooshie
Diamond Member
Nope.
Don't agree with BurntKooshie, see the post on Athlon 4 grossly outperfoming the classic TBird in Seti@Home ( TBird 1400 about 5:20h; Athlon 4 MP 1400 about 3:00h)
So the Athlon 4 should be better in doing RC5 too, although I know Seti is much more dependent on fast memory and a big L2 cache than RC5 is.
So the Athlon 4 should be better in doing RC5 too, although I know Seti is much more dependent on fast memory and a big L2 cache than RC5 is.
Hawkeye_(BEL)
Banned
They shouldn't be any faster, since most of the core, and this also means the integer units, is unchanged.
Data prefetch, huge Table Lookaside Buffers and SSE might be nice for S@H, but RC5 only needs raw integer performance; and the Pally still has the same 3 integer pipelines as it's older brother the TBird.
Data prefetch, huge Table Lookaside Buffers and SSE might be nice for S@H, but RC5 only needs raw integer performance; and the Pally still has the same 3 integer pipelines as it's older brother the TBird.
BurntKooshie
Diamond Member
cnhoff - Memory performance is practically a non-issue with RC5. It fits inside 8Kb L1 cache's (well, 16Kb, at any rate, in a Harvard Architecture). S@H and RC5 are TOTALLY different beasts. RC5 makes exclusive use of the ALU's, and is heavily reliant upon the bit-wise rotate left instruction.
S@H benefits from a low latency memory hierarchy, and strong FPU performance. The Athlon4/MP has both improved as compared to the T-bird, due to hardware prefetch (lowers average memory latencies due to increasing the hit-rate of the on-die caches when seeking instructions), and, potentially, due to the inclusion of SSE (I don't know how much, if at all, the S@H client is optimized for SSE). The improved TLB's also help to reduce memory latency.
RC5 does not benefit from the improvements made in the Athlon4/MP.
S@H benefits from a low latency memory hierarchy, and strong FPU performance. The Athlon4/MP has both improved as compared to the T-bird, due to hardware prefetch (lowers average memory latencies due to increasing the hit-rate of the on-die caches when seeking instructions), and, potentially, due to the inclusion of SSE (I don't know how much, if at all, the S@H client is optimized for SSE). The improved TLB's also help to reduce memory latency.
RC5 does not benefit from the improvements made in the Athlon4/MP.
BurntKooshie
Diamond Member
Seti makes good use of the new Athlon4/MP skills 😉
seti@home does not use SSE.
oh, and the bitwise rotate left is not a double pumped instruction on the pentium 4, very few are, actually (according to an intel guy who answered some questions about it at our CS dept.). so it takes a whole 4 cycles. instead of the 1 that p3 and athlon do it in.
oh, and the bitwise rotate left is not a double pumped instruction on the pentium 4, very few are, actually (according to an intel guy who answered some questions about it at our CS dept.). so it takes a whole 4 cycles. instead of the 1 that p3 and athlon do it in.
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