ASML enabling Moore’s law scaling and cost reduction out to 1 to 2 nanometers in mid-2020s

[goldstone77]

ASML enabling Moore’s law scaling and cost reduction out to 1 to 2 nanometers in mid-2020s
brian wang | July 20, 2017

T

oday ASML is selling billions in Extreme Ultraviolet lithography machines. These machines will help deliver chips at the 5 nanometer to 2 nanometer nodes.

ASML (Veldhoven, the Netherlands) sold eight more EUV (next-generation extreme ultraviolet lithography) systems in the second quarter. This brings its EUV backlog to 27 tools valued at about 2.8 billion euro (about $3.26 billion). The firm also announced that it demonstrated the key productivity metric of 125 wafers per hour (125) on an EUV tool at its headquarters.

Second quarter sales increased to 2.1 billion euro (about $244) million, up 8 percent compared to the year ago quarter. The company said it is on track to grow sales about 25 percent this year. Intel, Samsung and TSMC, are hoping to insert oft-delayed EUV lithography into volume production in the next two years.

ASML has a presentation that describes how they see EUV enabling a scaling push with lowering costs out to 2 nanometers.

 

[Ghidorable]

2nm, great how are you going to confirm features? Maybe by 2022 they'll have a decent ability to view and measure the nodes they put down, but 2 seems unreal to me.

 

[IntelUser2000]

2nm, great how are you going to confirm features? Maybe by 2022 they'll have a decent ability to view and measure the nodes they put down, but 2 seems unreal to me.

It never mattered in the first place. If 2nm offers roughly square of 2/3 space over 3nm, then at no point they'll be lying. Some companies will just use newer numbers purely to indicate that it is a change.

To answer ASML.

Why should it stop now?

Because pre-2000 people believe GHz scaling will go forever and we'd have 20GHz CPUs 5 years ago. Even before theoretical limits practical limits stop it from going. It will nevertheless improve, but it won't be "Moore's Law Scaling" and smaller transistors.

 

[whm1974]

Much better designs?

 

[goldstone77]

2nm, great how are you going to confirm features? Maybe by 2022 they'll have a decent ability to view and measure the nodes they put down, but 2 seems unreal to me.

I believe they refer to the thickness of the nano wire measuring ~1nm from UC Berkeley. Look under logic device and shrink roadmap.

Edit:
The world's smallest transistor is 1nm long, physics be damned
By Chaim Gartenberg@cgartenberg Oct 6, 2016, 3:34pm EDT

 

[VirtualLarry]

Because pre-2000 people believe GHz scaling will go forever and we'd have 20GHz CPUs 5 years ago.

But is this because of materials-science reasons, or cost reasons? Because, I thought that IBM (?) demonstrated a transistor that could switch at THz frequencies.

 

[goldstone77]

But is this because of materials-science reasons, or cost reasons? Because, I thought that IBM (?) demonstrated a transistor that could switch at THz frequencies.

DAILY NEWS
11 April 2005
World’s fastest transistor operates at blinding speed
By
Will Knight

The world’s fastest transistor has been developed by a pair of US researchers, possibly paving the way for a new generation of super-charged electronic chips.

Milton Feng and Walid Hafez at the University of Illinois at Urbana-Champaign, developed the record-breaking transistor by carefully blending different semiconducting materials within individual layers of the microscopic device.

Transistors are basic components within electronic circuits. They are used as tiny electronic switches or current amplifiers or for a variety of other tasks. Modern computer chips – like Intel’s Pentium 4 – contain millions of individual transistors and the fundamental efficiency of these chips depends on the speed at which their transistors operate.

Feng and Hafez developed a transistor less than half a millionth of a metre long, with a maximum operating speed of 604 GHz, meaning it can carry out 604 billion operations every second.

“This establishes a new benchmark for transistor performance,” says Doug Barlage at North Carolina State University, US. “It is probably three times faster than the fastest silicon-based device.”

Edit: Previously,
IBM claims 210-GHz SiGe transistor is world's fastest, four years ahead of competition
EE Times
6/25/2001 09:42 AM EDT

EAST FISHKILL, N.Y.--IBM Corp. today announced development of a new silicon-germanium (SiGe) transistor, which is capable of reaching speeds of 210 GHz while drawing only a milliamp of electrical current.

 

[imported_bman]

So is EUV finally going to be used in production within the next five years? Some people have been waiting a very long time:

https://forums.anandtech.com/thread...ving-the-way-for-smaller-faster-chips.477208/

Edit: lol, Adul is still an active member here

 

[goldstone77]

So is EUV finally going to be used in production within the next five years? Some people have been waiting a very long time:

https://forums.anandtech.com/thread...ving-the-way-for-smaller-faster-chips.477208/

Edit: lol, Adul is still an active member here

Samsung has been the first to adopt EUV, and will use it next year for 7nm production.

Edit:
Samsung Says EUV on Schedule for 2018
Dylan McGrath
9/12/2017 00:01 AM EDT

Samsung said it has processed close to 200,000 wafers with EUV lithography technology since 2014 and has recently seen visible improvement with EUV technology, such as achieving 80 percent yield for 256 Mb SRAM.

 

[goldstone77]

Samsung Unveils Scaling, Packaging Roadmaps
Foundry unit rolls out ambitious plan down to 4nm, along with 18nm FD-SOI and advanced packaging developments.
MAY 24TH, 2017 - BY: ED SPERLING

Low said that with EUV the company is turning out 1,200 wafers per day, and he expects that number to improve.

That's getting close to the magical 1,500 wafer per day!

 

[Lodix]

Samsung Unveils Scaling, Packaging Roadmaps
Foundry unit rolls out ambitious plan down to 4nm, along with 18nm FD-SOI and advanced packaging developments.
MAY 24TH, 2017 - BY: ED SPERLING


That's getting close to the magical 1,500 wafer per day!

This is from 24th of May.

 

[goldstone77]

This is from 24th of May.

It did but it adds to the discussion about EUV, and how close it is to being implemented. Samsung is supposed to use EUV to make 7nm this year. Hitting 1500 wafer per day is the magic number for production.

 

[ksec]

DAILY NEWS
11 April 2005
World’s fastest transistor operates at blinding speed
By
Will Knight


Edit: Previously,
IBM claims 210-GHz SiGe transistor is world's fastest, four years ahead of competition
EE Times
6/25/2001 09:42 AM EDT

While i knew at the time it wont be another 5 or 10 years before we see those in market. I was , really expecting Ghz to go on with better material science. Fast forward 15 years we are still stuck at the same Ghz barrier with no improvement in sight.

For my usage I dont know how i could put 16 Core to use, ( I could do only do 8 sometimes, at that is 16 threads. ), But I know I could use a 8Ghz CPU from time to time.

Why aren't more research going in this direction? Or is replacing silicon at a higher speed not worth the effort? It seems we are moving in direction where we have specific transistor doing jobs 10x faster then CPU rather then moving the CPU 10x faster.

 

[Tuna-Fish]

But is this because of materials-science reasons, or cost reasons? Because, I thought that IBM (?) demonstrated a transistor that could switch at THz frequencies.

DAILY NEWS
11 April 2005
World’s fastest transistor operates at blinding speed
By
Will Knight


Edit: Previously,
IBM claims 210-GHz SiGe transistor is world's fastest, four years ahead of competition
EE Times
6/25/2001 09:42 AM EDT

Note that transistors are already switching at speeds that corresponds to ~200 GHz frequencies in modern CPUs. A CPU needs all the individual transistors on it's longest logic chain to switch in series in the time of a single CPU cycle. A hypothetical CPU with a logic depth of 20 FO4 would therefore need to have transistors that are individually capable of 100 GHz operation just to run at 5GHz. In addition, the benchmark in CPU making is FO4, or a transistor with a single input driving 4 outputs, while those world's fastest transistors are probably measured with a single input and output. A FO4 transistor typically runs at less than half the speed of a single-output transistor.

 

[misuspita]

http://blog.electronica.de/en/2016/12/09/world-record-with-frozen-transistors/

Together with Analog Devices, IBM produced the first commercial products using SiGe (silicon-germanium) bipolar transistors in 1994. At the time—in the infancy of silicon-germanium technology—the maximum switching speed that could be reached was “just” 100 GHz (100 billion cycles per second). The era of world records started after that. And IBM, the Georgia Institute of Technology or the Leibniz Institute for Innovative Microelectronics (IHP) all had a finger in the pie.



2001 Conexant Systems Inc. got the ball rolling in 2001 with SiGe processing technology for transistors with switching frequencies up to 180 GHz.

2002 Just one year later, IBM took back the laurel wreath with cycle times of 350 GHz for SiGe transistors that were manufactured in a 9HP BiCMOS process.

2006 In mid-2006, IBM and the Georgia Institute of Technology took things to the next level and operated SiGe transistors on 200-millimeter wafers at 500 GHz at near absolute zero. They reached nearly 350 GHz at room temperature.

2014 After that, IHP and the Georgia Institute of Technology made the record books with a maximum frequency of 798 GHz—also under “ice cold” conditions near minus 273 degrees Celsius. With speeds of 417 GHz at room temperature, the SiGe transistor is still significantly faster than 98 percent of all currently available transistors. The heterojunction bipolar transistor (HBT) designed by IHP and manufactured using a 130-nm BiCMOS process was made out of a silicon-germanium nanoalloy and embedded in a silicon transistor.

2016 And now in early December, once again IHP announced another heterojunction bipolar transistor that operates at a maximum frequency of 720 GHz at room temperature. The new world record was the result of the DOTSEVEN project funded by the EU. Participants included IHP, Infineon and twelve other partners from six countries. The next SiGe target: the terahertz barrier, what else

https://www.electronicsweekly.com/news/research-news/us-claims-thz-transistor-speed-record-2014-10/

Developed for US military lab DARPA, the ten-stage common-source amplifier showed 10dB gain at 1.0THz and 9dB at 1.03THz. The transistors are 25nm gate length indium phosphide (InP) HEMTs.

https://www.eetimes.com/document.asp?doc_id=1327330

Purdue University researchers have demonstrated a CMOS-compatible all-optical transistor capable of 4THz speeds, potentially over a 1000 times faster than silicon transistors.

Nano-photonic transistors processed at low-temperatures can be fabricated atop complementary metal oxide semiconductors (CMOS) to boost switching time by ~5,000-times less than 300 femtoseconds (fs) or almost 4 terahertz (THz), according to researchers at Purdue University.

Actually we have 1THz transistors, but not at room temperature.

 

[goldstone77]

While i knew at the time it wont be another 5 or 10 years before we see those in market. I was , really expecting Ghz to go on with better material science. Fast forward 15 years we are still stuck at the same Ghz barrier with no improvement in sight.

For my usage I dont know how i could put 16 Core to use, ( I could do only do 8 sometimes, at that is 16 threads. ), But I know I could use a 8Ghz CPU from time to time.

Why aren't more research going in this direction? Or is replacing silicon at a higher speed not worth the effort? It seems we are moving in direction where we have specific transistor doing jobs 10x faster then CPU rather then moving the CPU 10x faster.

I think you have to think about power draw, heat, size, cost. RF circuits operate upward of 25GHz. We could make a faster CPU, but you would have to make it big, drawing more power, and creating enormous amounts of heat. It's just not economically viable to make one. Cell phones use specialized processors for low power and high power. Usually 2 or 4 cores low power and 2 or 4 core high power. I think we will eventually have specialized CPU incorporated on the die to perform specialized functions like ASIC. At some point A.I. will start designing CPU's and software, and we will probably see an evolutionary change in computing in direction human beings won't be able to understand. But who knows how close or far away that is.
science and technology
Silicon-Germanium Chip Sets New Speed Record
FEBRUARY 18, 2014 • ATLANTA, GA

Cressler and his team demonstrated the 800 GHz transistor speed at 4.3 Kelvins (452 degrees below zero, Fahrenheit). This transistor has a breakdown voltage of 1.7 V, a value which is adequate for most intended applications.

The 800 GHz transistor was manufactured using IHP’s 130-nanometer BiCMOS process, which has a cost advantage compared with today’s highly-scaled CMOS technologies. This 130 nm SiGe BiCMOS process is offered by IHP in a multi-project wafer foundry service.

The Georgia Tech team used liquid helium to achieve the extremely low cryogenic temperatures of 4.3 Kelvins in achieving the observed 798 GHz speeds. "When we tested the IHP 800 GHz transistor at room temperature during our evaluation, it operated at 417 GHz," Cressler said. "At that speed, it's already faster than 98 percent of all the transistors available right now."

Note that transistors are already switching at speeds that corresponds to ~200 GHz frequencies in modern CPUs. A CPU needs all the individual transistors on it's longest logic chain to switch in series in the time of a single CPU cycle. A hypothetical CPU with a logic depth of 20 FO4 would therefore need to have transistors that are individually capable of 100 GHz operation just to run at 5GHz. In addition, the benchmark in CPU making is FO4, or a transistor with a single input driving 4 outputs, while those world's fastest transistors are probably measured with a single input and output. A FO4 transistor typically runs at less than half the speed of a single-output transistor.

I think you have to think about power draw, heat, size, cost. RF circuits operate upward of 25GHz. We could make a faster CPU, but you would have to make it big, drawing more power, and creating enormous amounts of heat. It's just not economically viable to make one.

 

[Andrei.]

Note that transistors are already switching at speeds that corresponds to ~200 GHz frequencies in modern CPUs. A CPU needs all the individual transistors on it's longest logic chain to switch in series in the time of a single CPU cycle. A hypothetical CPU with a logic depth of 20 FO4 would therefore need to have transistors that are individually capable of 100 GHz operation just to run at 5GHz.

Good god that's not how it works. They're cascading transistors with propagation and switching delays between them, they're not actually switching at a higher rate. They're still operating at CPU frequency.

 

[Tuna-Fish]

Good god that's not how it works. They're cascading transistors with propagation and switching delays between them, they're not actually switching at a higher rate. They're still operating at CPU frequency.

They of course only switch whenever their control input switches, so if the control input only switches once they only switch once per clock cycle. However, in order for the CPU to be able to maintain it's clock rate, each of the transistors on a critical path only have a fraction of the time of the clock cycle to switch, so if they were instead made to switch states as quickly as possible (which is what that IBM research paper did), they would have to be able to reach at least a speed of CPU clock rate * cpu logic depth.

 

[LightningZ71]

[this is vastly simplified for anyone non-technical following the thread]

I was always under the impression that instructions were "in flight" over multiple clock cycles down the instruction pipeline. The "Ghz" rating of the processor basically indicated the rate at which the processor was able to issue new instructions down the pipeline, kind of like a conveyor belt that moved at a certain speed and had designated package slots. The belt is pushing a slot past at (5Ghz) 5 billion slots a second. As long as the issue logic has an instruction ready to go, an instruction can be sent down the conveyor. (this is obviously an over simplification as power management and thermal throttling can slow the speed of the belt). The processor (belt path) has so many points where the item in each slot is worked on (pipeline stages). Once the end of the conveyor assembly has been reached (instruction retirement), the belt loops back around to start again and the results of the instruction are addressed by the memory management unit. The time it took to make it down the conveyor belt path takes a fixed amount of stations (instruction latency as a function of clock cycles between issue and retirement) and many new packages will have been placed on the belt behind the first one so that all can be worked on at once. Some processors have the conveyor belt split into multiple smaller ones along the way (multiple pipelines) and sometimes conveyor belts have to stop (dump their instructions due to branch mispredict) and start over again with the same packages, or different ones because of something that happened with an earlier package. Some factories have many large conveyor assemblies (multiple core processors) and some conveyor belts can have packages fed by multiple package placers (multi-threading).

The reason that Ghz rating has had so much less meaning lately than it used to is because of how complex CPUs have become. They can potentially retire several instruction per core per cycle in some circumstances while other instructions are some complex that the processor can run many, many cycles before they are retired. What makes higher rated chips so impracticle is that the power curve is not linear. Once you leave the sweet spot of a given process node, power consumption and heat production goes through the roof as processors are pushed to higher switching speeds. The current nodes for volume production are optimized more for density (more chips per wafer, higher economies of scale) and less for flattening out the curve as frequency scales. This is, of course, not to say that there aren't other processes out there that are focused on lower power, lower heat, and higher frequencies instead of density. IBM has one that's optimized for frequency (that is currently owned/produced by GloFo) and gives them 5+ ghz production chips (in low quantities and VERY high prices). However, with those prices, it would basically be unsellable in the mass market and can't currently be scaled up in volume enough to make economic sense.

I've never heard that the individual gates in the processor were running at many multiples of the indicated maximum "processor speed" rating, with the exception of certain specialized control chips and signal processors. However, I am always open to new information and am willing to be corrected.

 

[Tuna-Fish]

Think of what happens inside a single pipeline stage. You start with the outputs of the previous stage in flip-flops (A flip-flop, or sometimes latch, is one of the most fundamental building blocks of digital circuits. It is a storage device with two inputs, DATA and CLOCK which steadily outputs its stored value until the CLOCK signal is raised, at which point it reads DATA into it's stored value and starts outputting that.), and you end with the output of your stage fed into the DATA lines of the latches of the next pipeline stage.

In between, you do whatever that stage does to the inputs in a chain of transistors, each using the output of the previous as the control of the next. Ideally, each transistor on the logic path only switches at most once during a clock cycle (as active power is only consumed and heat generated when the state of a transistor switches), but doing any useful work requires chaining many transistors after each other. (For example, in a simple full adder the signal needs to sequentially propagate through 3 logic gates to reach the carry, or if you implement it in pure nand you need 6 gates for the value.)

The maximum stable clock speed of a CPU is the speed at which the delay between triggering the clock signals is the lowest it can be so that a signal traveling every signal path in every stage of the CPU can reach the data input of every latch in the CPU before the clock changes again. As each transistor in these chains has much less time to switch than the full CPU cycle, they need to be capable of higher performance than "switch once per CPU clock cycle"-

 

[goldstone77]

The AMD Zen and Ryzen 7 Review: A Deep Dive on 1800X, 1700X and 1700
by Ian Cutress on March 2, 2017 9:00 AM EST

Arguably you can make a massive core design to run at high performance and low latency, but it comes at the expense of die size which makes the cost of such a design from a product standpoint less economical (if AMD had to rely on 500mm2 die designs in consumer at 14nm, they would be priced way too high).

Which is basically what I was saying if you scroll up.

We could make a faster CPU, but you would have to make it big, drawing more power, and creating enormous amounts of heat. It's just not economically viable to make one.