Article on hammer's extra stages.

[Adul]

link

Two new pipeline stages are added to the pipeline. They are inserted directly after the stage where the x86 instructions have been either decoded, ( In case of the simpler 'RISC' like x86 instructions), or have started the micro code program from the micro code ROM. ( In the case of the more complex 'CISC' like x86 instructions) The new pipeline stages thus receive a stream of decoded instructions, either from the decoders or from the micro code ROM.

 

[formulav8]

So would that be 12 or 14 now?

 

[Adul]

12

 

[formulav8]

We already knew about hammer having 12 stages. Why is this news? I thought they added 2 more to make 14.

 

[BD231]

Originally posted by: formulav8
We already knew about hammer having 12 stages. Why is this news? I thought they added 2 more to make 14.

Yes we did already know, but we did not have anything this in depth about the new stages.

 

[ST4RCUTTER]

As usual, Chip Architect makes for a damn fine read.

 

[andreasl]

The interesting part of this is that it looks like Hammer won't clock higher than the K7 simply because it has 2 extra pipe stages. This because the extra stages also adds extra logic not found in the K7. But AMD could still have done other things to increase it's clockspeed somewhat. SOI being the most obvious one.

 

[Adul]

hammer will be fab on soi.

 

[MadRat]

Is this strategy in parrallel to Intel's L1 cache on the Pentium4?