Originally posted by: EdipisReks
if you read the discussion over at ars about the review, you'll find your view about who is at fault for the G4 bus to not be totally accurate. personally, i can't wait for 970 based powerbooks.
Well, I went thru that
Ars thread, and the only thing really mentioned was:
"
Thus, Apple has been forced to come up with their own memory controller for the G4, lest they be stuck with the previous generation's terrible SDR stuff. At worst their offerings are a pointless marketeing-inspired hack, and at best they're a brilliant stopgap measure. IN any case, Apple is trying their best to make do with motorola's offerings, but the point remains that Apple, not motorola, designed the current setup."
and
"
Narrowly speaking, true. But in CPUs, as in all other things ... you get what you pay for... IF you are a savvy buyer.
Grafting a faster FSB onto the G4+ core would not have been unreasonably hard... if Apple wanted to pay for it. A big part of the problem is that APPLE didn't give a rip about memory bandwidth back in the days when the MPXbus wasn't the limiting factor... Apple was always late with better memory bandwidth ... and by the time the situation got really, really embarrassing Apple needed more than just a G4+ with some more bandwidth, it needed a whole new CPU architecturally... sooooo ..."
What that suggest to me is that my contention that the current G4 cannot (properly) make use of a DDR bus is still valid.
It would take a new chip design. That chip would be
7457-RM, but alas, it does not yet exist. It sounds like from the above argument is that Apple simply didn't pay Motorola enough to make that design change earlier. Given Motorola's focus on the embedded market and track record with Apple, I can understand why Apple would balk at this.