[Ars Technica] IBM and the 7 nm breakthrough
- Thread starter Mondozei
- Start date
Usually in the foundry market what counts is lots of production silicon delivered in a timely fashion accompanied of very high yields. This press release is far, far away from that.
NTMBK
Lifer
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sm625
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From the article:
What are these guys smoking? Where can I buy a 14nm graphics card? 7nm in two years? Ha! We'll be lucky to see 14nm in two years at this rate. Why are graphics being pooped on so heavily these days? The best video cards produced today cannot even run 4K games at 60fps.
What are these guys smoking? Where can I buy a 14nm graphics card? 7nm in two years? Ha! We'll be lucky to see 14nm in two years at this rate. Why are graphics being pooped on so heavily these days? The best video cards produced today cannot even run 4K games at 60fps.
NTMBK
Lifer
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High end cellphone processors are where the money is these days. Apple has been at 20nm since September last year, Samsung's been shipping a 14nm processor for months.
From the article:
Regardless, I still think it's cool they they already have test dies on 7 nm. And the more competition we get the better.
Can IBM really manage to roll out 7 nm in 2017/2018? That would be around the same time as Intel/TSMC is expected to provide 10 nm.
Regardless, I still think it's cool they they already have test dies on 7 nm. And the more competition we get the better.
Ok, so you're suspecting IBM will "sell" the IP rights to someone else who will make actual products from it? Any chance that "someone else" (Intel/TSMC/Samsung/[...]) will be able to make products based on that in 2017/2018?
They do make a lot of money off their IP. Their vast IP resources are always why they are very rarely involved in serious patent disputes or attacked by patent trolls. Basically, anybody involved in tech is probably violating an IBM patent on some level. And they all know it.
shady28
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IBM has been spitting out patents for decades. In fact, they've been granted more patents every year than any other company for 22 years. They spend > $6 Billion / yr on R&D and take in over $1 Billion / yr in patent licensing.
You can bet that whatever tech they've developed is for sale. They really aren't that interested in manufacturing anymore, it's all about services and IP.
sm625
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Yeah but what gets me is that graphics chips are the easiest things to design. They are heterogenous. Their power requirements dont matter all that much. They should be the first on a node. Smartphone SoCs are monstrously complex in comparison. I cant wait for people to stop paying $600 for smartphones. It is such a waste of money and it drags everything else down. I guess what we need is for AMD or Nvidia to start releasing a monster GPU on a two year idiot plan like all the cell carriers do.
SAAA
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I'm in.
No for real, where's my 15/month, 2 years plan for a high end video card + monthly games? :sneaky:
WhoBeDaPlaya
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myocardia
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Easy to design does not mean easy to fab, though.
Small die area means easy to fab, and the SOCs in $600 phones are many times smaller than the GPUs that nVidia and AMD have fabbed.
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myocardia
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We need to get IDC in here since he's a process guy
I know, right? Anyone have the slightest idea what time it is in 台北市?
Phynaz
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We need to get IDC in here since he's a process guy
Do you interface with the process teams at all?
I am wondering if I read this correctly:
So they are using EUV which supposedly has long exposure times due to output power problems from the light source through the mask to the wafer, and they are quad-patterning it? Are they using the term "quad-patterning" to mean that they are using four different masks for each layer and then exposing each one? With a 13nm light source why do they need to quad-pattern a 7nm feature size? And how long would that actually take in a real fab? Everyone is moaning about double-patterning using a 193nm light source on 20nm and smaller and the effect on throughput (and thus on cost). I thought one of the wonderful things about EUV was that you could get rid of double-patterning, but if this article is to be believed (and I'm reading it correctly) they are actually taking a much slower lithography patterning machine (EUV) and then using four masks per layer... which seems like it would take so long that it never be commercially viable... and I'm not sure that I understand why you even need to do anything this complex.
Anyway, it's interesting.... it just seems perplexingly complex and extremely far from commercialization in a high volume fab that needs higher wafer throughput to maintain cost effectiveness.
As always, I am not speaking on behalf of my employer, and my opinions are my own.
As background reading, this link talks about the problems of exposure times on EUV:
http://spectrum.ieee.org/semiconductors/devices/euv-chipmaking-inches-forward
and this one talks about the talks about the way node sizes are named - something that IDC has been talking about for years but I only finally understood what he was saying fairly recently - and problems at 14nm and below:
http://spectrum.ieee.org/semiconductors/devices/the-status-of-moores-law-its-complicated
And by the way, while I'm posting up about EUV, I would just like to point out that the way that the light source is made - by dropping molten tin into a high power laser beam which vaporizes the tin and creates 13.5nm ultraviolet light seems completely crazy to me. I understand that this is where the industry is headed, but as a source of light dropping molten metal into a laser beam while you have a jet of hydrogen gas to steer the drops seems completely Rube-Goldbergian to me. It might be practical, it might be necessary, but it still seems like "you have to be kidding me... really? that's the way it works?".
So they are using EUV which supposedly has long exposure times due to output power problems from the light source through the mask to the wafer, and they are quad-patterning it? Are they using the term "quad-patterning" to mean that they are using four different masks for each layer and then exposing each one? With a 13nm light source why do they need to quad-pattern a 7nm feature size? And how long would that actually take in a real fab? Everyone is moaning about double-patterning using a 193nm light source on 20nm and smaller and the effect on throughput (and thus on cost). I thought one of the wonderful things about EUV was that you could get rid of double-patterning, but if this article is to be believed (and I'm reading it correctly) they are actually taking a much slower lithography patterning machine (EUV) and then using four masks per layer... which seems like it would take so long that it never be commercially viable... and I'm not sure that I understand why you even need to do anything this complex.
Anyway, it's interesting.... it just seems perplexingly complex and extremely far from commercialization in a high volume fab that needs higher wafer throughput to maintain cost effectiveness.
As always, I am not speaking on behalf of my employer, and my opinions are my own.
As background reading, this link talks about the problems of exposure times on EUV:
http://spectrum.ieee.org/semiconductors/devices/euv-chipmaking-inches-forward
and this one talks about the talks about the way node sizes are named - something that IDC has been talking about for years but I only finally understood what he was saying fairly recently - and problems at 14nm and below:
http://spectrum.ieee.org/semiconductors/devices/the-status-of-moores-law-its-complicated
And by the way, while I'm posting up about EUV, I would just like to point out that the way that the light source is made - by dropping molten tin into a high power laser beam which vaporizes the tin and creates 13.5nm ultraviolet light seems completely crazy to me. I understand that this is where the industry is headed, but as a source of light dropping molten metal into a laser beam while you have a jet of hydrogen gas to steer the drops seems completely Rube-Goldbergian to me. It might be practical, it might be necessary, but it still seems like "you have to be kidding me... really? that's the way it works?".
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for a research chip, you only have to find one transistor out of a trillion that works.
for a commercial chip, you have to make sure pretty much every transistor works.
IBM = no SOI anymore ?
for a commercial chip, you have to make sure pretty much every transistor works.
IBM = no SOI anymore ?
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shady28
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Some questions answered here :
http://blog.timesunion.com/business/a-look-at-ibms-new-7nm-chip-wafer-made-in-albany/67677/
http://blog.timesunion.com/business/a-look-at-ibms-new-7nm-chip-wafer-made-in-albany/67677/
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