ARM announces 2GHZ -Dual Core Processor

[IntelUser2000]

Motorola claims a 2GHz Tegra part. Considering how the Tegra 2 devices aren't even out yet, its likely that they are calling dual core 1GHz as "2GHz".

 

[aphorism]

So how much power differences do you think exists between x86 and RISC? Let's see what you think of it. 50%? 2x? 10x?

2-3x would be a good guess although we are going through another ISA philosophy transition so it is becoming irrelevant. it is a very hard comparison because the two main x86 manufacturers have huge R&D budgets. intel could make an extremely fast RISC processor but it would open up room for competition thus lower margins. also they tried creating a new ISA and it didnt work out so well (in terms of revenue).

specint_rate: POWER7 v. nehalem EX, 32 cores each.
http://www.spec.org/cpu2006/results/res2010q1/cpu2006-20100315-09869.html759
http://www.spec.org/cpu2006/results/res2010q1/cpu2006-20100208-09580.html1,460

specfp_rate: POWER7 v. nehalem EX, 32 cores each.
http://www.spec.org/cpu2006/results/res2010q2/cpu2006-20100331-10342.html554
http://www.spec.org/cpu2006/results/res2010q1/cpu2006-20100208-09585.html1,300

i am not sure about the budget of IBM's microelectronics division but i dont think it is as large as intel's. their manufacturing processes are about as fast as intel's but generally have higher wafer costs.

 

[IntelUser2000]

Aphorism, I don't think quoting those two are exactly favorable to the RISC vs x86 discussion. Xeon 7560 is at 130W TDP while the Power 7 model you quoted is at 200W. Power 7 also has twice as much memory bandwidth and I/O bandwidth that can't be compared to the Xeon. Meaning some of the advantages are due to the Platform not the ISA.

The 0.18u Itanium 2 "Mckinley" outperformed the predecessor 0.18u Itanium "Merced" by 2x and had similar TDP figures. The Mckinley, with significantly enhanced core didn't increase die size much over Merced, even though the former included 3MB L3 SRAM on die. Mckinley also out-clocked Merced by 25% while reducing pipeline stages by 20%.

Did the ISA change? No.

RISC might be ahead, but not something to the degree that can't be overcome. Intel also has a better process tech even at same xx node.

their manufacturing processes are about as fast as intel's but generally have higher wafer costs.

Doubt that. It's not only a year behind which contributes to the differences but they are in alliance with GF and such.

 

[cbn]

http://www.anandtech.com/show/3844/ti-first-to-license-arms-nextgeneration-eagle-core

Eagle’s performance is slated to be much more competitive with future derivatives of Intel’s Moorestown SoC, while power consumption should be similar to existing designs thanks to the 2x-nm manufacturing process it will most likely be built on.

Is this being called Eagle because it is a single core? (ie, Lone Eagle) in contrast to the 2 Ghz dual core Cortex A9 mentioned in this thread.

If so, that would make for some interesting discussions/comparisons to Moorestown (or more likely Medfield) which AFAIK is also single core.

EDIT: After doing some re-reading, I am wrong about by guess of "Eagle" being a single core variant of "A9".

 

[IntelUser2000]

The Eagle core is something like 2013+.

 

[aphorism]

Aphorism, I don't think quoting those two are exactly favorable to the RISC vs x86 discussion. Xeon 7560 is at 130W TDP while the Power 7 model you quoted is at 200W. Power 7 also has twice as much memory bandwidth and I/O bandwidth that can't be compared to the Xeon. Meaning some of the advantages are due to the Platform not the ISA.

The 0.18u Itanium 2 "Mckinley" outperformed the predecessor 0.18u Itanium "Merced" by 2x and had similar TDP figures. The Mckinley, with significantly enhanced core didn't increase die size much over Merced, even though the former included 3MB L3 SRAM on die. Mckinley also out-clocked Merced by 25% while reducing pipeline stages by 20%.

Did the ISA change? No.

your example isnt exactly fair either. merced was a rushed, unfinished processor. improving upon it was not hard, all they needed was time. another thing i have never understood about itanium is that they use domino gates throughout the entire pipeline. that's not a good choice for something that should be robust. yes, it allows for less pipeline stages but it's not worth it on modern processes.

i'm just showing that RISC is still beating x86 today, as it was 20 years ago. designing faster uarch is still easier for RISC(everything is easier to design with risc but not to the degree that uarch is). in fact almost all x86 processors translate native instructions into RISC instructions internally. it makes it a lot easier to do OoO and reg renaming.

RISC might be ahead, but not something to the degree that can't be overcome. Intel also has a better process tech even at same xx node.

even spending shitloads of money on process engineering and design teams RISC's advantages are still there. it is extremely difficult to polish poo.

Doubt that. It's not only a year behind which contributes to the differences but they are in alliance with GF and such.

you'd be surprised.

 

[cbn]

http://en.wikipedia.org/wiki/MeeGo#Software_development

One thing that has me concerned about Moorestown is software development. Looking under "Release schedule" it still appears Meego is a netbook OS.

 

[cbn]

even spending shitloads of money on process engineering and design teams RISC's advantages are still there. it is extremely difficult to polish poo.

At what point does Intel decide to create its own RISC design? After some brief reading (and when I say brief, I mean extremely brief) seems to indicate Intel has done quite a bit of experimentation with 3D chip design.

Wouldn't a 3D design allow Intel to make higher gains in efficiency with less material needed?

In contrast, when I looked at this this Apple A4 CPU dissection I was quite shocked it had die size of 53mm2. That strikes me as quite a bit of silicon for a product that barely uses any energy.

 

[DrMrLordX]

Intel tried to one-up the RISC guys with VLIW and that doesn't seem to have worked out too well for them.

Their highest-profile GPU(ish) design effort, Larrabee, involved numerous die-shrunk p54c cores with vector instructions sort of tacked on. Call me crazy, but I wouldn't take that as an indicator that they're seriously looking at RISC designs anywhere.

It's not to say that Intel hasn't had RISC designs in their portfolio before (i860, i960, StrongARM, Xscale).

 

[cbn]

Intel tried to one-up the RISC guys with VLIW and that doesn't seem to have worked out too well for them.

Their highest-profile GPU(ish) design effort, Larrabee, involved numerous die-shrunk p54c cores with vector instructions sort of tacked on. Call me crazy, but I wouldn't take that as an indicator that they're seriously looking at RISC designs anywhere.

It's not to say that Intel hasn't had RISC designs in their portfolio before (i860, i960, StrongARM, Xscale).

Thanks for letting me know about the history.

Yep, I have no clue what type of instruction set Intel would need to use.

I just think it would be cool to see them build a very tiny 3D design multipurpose processor that could seamlessly switch between high speed single threaded to highly parallel. Essentially it would be a low cost high performance device that would provide the highest bang for the buck to the most amount of people.

P.S. I brought up "3D" chip design because I am under the impression only Intel has the R&D budget to really pull it off.

 

[IntelUser2000]

you'd be surprised.

Surprise me.

RISC isn't beating x86, Power 7 is beating Xeon 7500, but with a much better platform and much higher TDP as well. There are disadvantages to x86, but its not big as most think. The increasing role that uncore components like I/O take on power and die also makes x86 vs RISC less and less significant.

In a 1991
study between VAX and MIPS, Bhandarkar and Clark showed that after canceling
out the code size advantage of CISC and the CPI advantage of RISC, the
MIPS processor had an average 2.7x advantage over the studied CISC processor
(VAX).

A 1997 study on Alpha 21064 and the Intel Pentium Pro still
showed 5% to 200% advantage for RISC for various SPEC CPU95 programs.

We find that the
SPEC CPU2006 programs are divided between those showing an advantage on
POWER5+ or Woodcrest, narrowing down the 2.7x advantage to nearly 1.0.

Our study points out that with aggressive micro-architectural techniques for ILP,
CISC and RISC ISAs can be implemented to yield very similar performance.

 

[aphorism]

Surprise me.

eDRAM: 2.7x smaller than intel's 45nm standard SRAM cell and 40% smaller than intel's 32nm standard SRAM cell. 7.9TB/s L3->L2 bandwidth.D:

they have done more chip stacking research and currently have the best TSV/mm2 of anyone.

their 45nm process uses the best low-k dielectric physically possible... a vacuum.

http://www.realworldtech.com/page.cfm?ArticleID=RWT072109003617&p=11

RISC isn't beating x86, Power 7 is beating Xeon 7500, but with a much better platform and much higher TDP as well. There are disadvantages to x86, but its not big as most think. The increasing role that uncore components like I/O take on power and die also makes x86 vs RISC less and less significant.

*various papers*

you are the only person i have ever talked to (or posted to, whatever you want to call it) that has thought x86 is as good as RISC. you really need to read the article i linked to earlier.

the ISA directly affects the platform. for example SSE performance is terrible if memory access is not aligned to 16 bytes. because of this bandwidth utilization can be very poor.

comparing to woodcrest to POWER5 is really expected from x86 proponents. they compare their architecture to others at the trough of the competitions performance and at their peak, when their next gen product releases. with performance doubling every 2 years its easy to make that number smaller. during most of that time IBM was focused on CELL which is currently in the majority of the GREEN500'S top 10 supercomputers and some 40million ps3's. purely intel based systems are only 2 of the top 10.

have noticed that power7 is 110mm2 smaller than beckton? most of these chips consist of interconnect and cache.

not to scale!!

 

[IntelUser2000]

x86 does have disadvantages but the disadvantages aren't 2-3x. Plus the reason for die size differences have to do with that Power 7 uses eDRAM and Nehalem EX uses SRAM. Yes its impressive that its a first commercial MPU to integrate eDRAM on CPU die.

But we are going far more than just x86 vs RISC.

 

[Phynaz]

RISC isn't beating x86, Power 7 is beating Xeon 7500, but with a much better platform

This.

I've never seen a $1M x86 system - and no, somebody doesn't have to link to some obscure system to prove they exist.

I'm running two $1M+ Power systems. What's built around the cpu is as important, if not more important than the cpu itself. x86 being relegated to commodity status, is never going to compete in the high end.

Oh, and those Power systems don't include our two Z9's and one Z10, which I believe also run Power cpu's, but that is another persons area of responsibility and I can't say for sure.

 

[theeedude]

I read this over on EETimes too, did anyone else notice they are stating clockspeed and power-consumption numbers for a design that has yet to be implemented into silicon?



This is the kind of sensationalism pre-release headline hype that just grinds my gears.

"W00t! 2GHz 1.9W Osprey A9 in the house bitches!"?


? the osprey A9 has not actually been fabricated in reality; silicon for the device does not exist, any and all claims of clockspeed and power consumption are the product of wishful hoping of Ted, our designated "water the plant every other week" guy who can't really be trusted with anything but making awesome headlines

(tongue in cheek of course, they do know the designed capabilities and can reasonably project power-consumption with the assumption that the fab process is hitting all the spec'ed parametrics, but touting design expectations as if they are verified functional silicon realities is just shoddy marketing gimmicks in my book)

It's not just marketing, this is a product designed from ground up to a specific power envelope. It's simulated data, on a mature process with well known parameters. ARM is selling IP that is designed to perform to spec. If a customer licenses that IP, invests in designing a product using it, and it does not perform to spec, there could be severe financial and PR consequences for ARM. So they are probably padding whatever power numbers they give to customers to account for process variation.

 

[Fjodor2001]

People have here have been talking about the problem of porting the Windows OS to ARM. But what about the problem of getting all Windows applications compiled for the ARM CPU? Aren't basically all Windows applications only available as x86/x64 binaries? There is no use having Windows running on an ARM CPU if there are no applications to run anyway...:\

 

[VirtualLarry]

People have here have been talking about the problem of porting the Windows OS to ARM. But what about the problem of getting all Windows applications compiled for the ARM CPU? Aren't basically all Windows applications only available as x86/x64 binaries? There is no use having Windows running on an ARM CPU if there are no applications to run anyway...:\

The PE (Portable Executable) binary format that all modern Win32 apps use, has "sections", and they can have different sections for different ISAs, thus essentially a "fat binary" (an Apple term).

 

[Fjodor2001]

Ok, I see. So it's technically possibly to have a Portable Executable that has sections for both e.g. x86 and ARM in the same executable file. The question is then of course if most Windows application actually has a section for ARM? If not, the problems with lack of Windows applications that can execute on ARM still remains, right?

 

[cbn]

Ok, I see. So it's technically possibly to have a Portable Executable that has sections for both e.g. x86 and ARM in the same executable file. The question is then of course if most Windows application actually has a section for ARM? If not, the problems with lack of Windows applications that can execute on ARM still remains, right?

Based on what was said in post #67 it sounds like Windows Apps can execute on ARM.

Can someone else clarify this?