are durons & t-birds smp capable?

[TuffGuy]

i think i remember from somewhere that the current durons and t-birds are already smp capable, the only thing needed is the future mobo chipset. am i correct? i'm thinking of picking up a couple of chips right now since they can still be found unlocked.

(i wanna run dual instance of seti...)

 

[A5]

Yes they are...just gotta wait for mobos

 

[TuffGuy]

SWEET!!!

 

[artemedes]

As soon as I heard AMD was working on a new chipset that was smp and capable of using DDR ram, I wanted one. I don't usually buy brand new technology, but a twin t-bird setup running 266mhz ddr ram just might pursuade me to try the latest. Can't wait to see my Seti times on this when I can build it.

 

[TuffGuy]

ok, i need some advice. should i buy the chips now, or wait for amd to lower cpu prices to try to steal intel's thunder?

 

[SilverBack]

News Flash!!!!!!!!!!
Did I Get your attention?
All Duron and Tbirds made today support SMP, you already knew that.
BUT what you may not know is that the current TBirds and Durons will only support the PC1600 standard or DDR at 200MHz ram. The PC2100 or 266MHz ( the bus runs the same speed )will need the new Mustang core.
It will still be fast though!!
Rumor has it that the PC2100 support won't happen until the first quarter 2001...

You know I'm sitting here trying to come with a reason why the TBirds and Durons won't work. The way the cpu's work now is that a GHZ cpu truly has a multiplier of 5. ( 5x200 EVA bus)
I'm pretty sure that a GHz cpu isn't going to work at 5x266
However the lower clocked cpu's may indeed just have enough umph to do it.
Consider, a 600 Duron will go 900. So 3x200 600 3x266=798. I think thats a sure bet unless it's just not pin compatible. So 3.25x266=864 and 3.5x266=931....
The 600 and 650 cpu's if pin compatible may just be sure winners for a dualy on a 266MHz bus!!!

 

[TuffGuy]

i think that the problem lies with the ev6. the fsb for durons and t-birds is 200mhz(2*100mhz). at the present time, you can only overclock the fsb to about 110Mhz, or 220mhz effective. for it to run at 266mhz(2*133mhz), some modifications have to be made.

 

[amok]

The new boards coming out will have support for the 133MHz DDR FSB. AMD's 760, Via's KT266, and I believe even ALi's new boards. With the new boards the memory bus and fsb are syncronous, so if you're running your FSB at 266 then your memory will run at 266. If you run your fsb at 200 then you're memory will run at 200. I believe that the only hope of getting current processors to run at the faster settings is to use the lower clocked cpus. You know Abit and Asus will have a host of options for these boards to make using PC2100 with the lower clocked cpus a reality .

However, I'm glad that the fsb and memory clock will be syncronous, because that will eliminate some of the memory latency that has been a problem with via and amd chipsets.

 

[Assimilator1]

Amok

>>>>However, I'm glad that the fsb and memory clock will be syncronous, because that will eliminate some of the memory latency that has been a problem with via and amd chipsets. <<<<

Are you sure thats what's been causing the higher latency? ,could you throw me somelinks about it?.
BTW I found the asyncronus mem bus useful for setting 133MHz mem bus for 100MHz (or 100MHz DDR) cpus

 

[SilverBack]

Actually the KT133 chipset from VIA has the highest memory bandwidth benchmarks that I have tested so far.
Using SiSoft Sandra
558/618

 

[RC]

Yes, Durons and TBirds are SMP capable but no mobo support for it currently.
Latest word is Jan/Feb for the AMD 760MP chipset mobos.

 

[Assimilator1]

Silverback

I don't doubt you ,however Sisoft doesn't measure latency ,(does it? or is it in m/brd info?)

 

[BurntKooshie]

latencies and bandwidth are intrinsically intertwined as far as real world performance is concerned (very very rarely do you have multi gigabyte files that are flying through in one continuous stream).

There is an added clock of latency if the memory timings are asyncronous (I believe its 8 clocks vs 7, but I'll have to double check on that). While that doesn't seem like a lot, remember that that is a 14.3 % jump from the perspective of 7 cycles. This is why a synchronous chipset such as the BX whoops on the VIA chip, because it is a synchronous VS. asynchronous design.

The asynchronous feature adds to the feature set becase even with a 100mhz FSB, you can still use PC 66 (slower because its PC 66, AND because of the 1 clock latency), which makes upgrading easier. You can also get more maximum bandwidth (ie, PC 133 @ 100mhz FSB), but in practice, this is only when very large data sets are being transfered all at once, because if there are many smaller ones, the extra latency kills it.

BK

[start Russ mode]
NCNE (so far)
[/end russ mode

 

[Assimilator1]

Thanks BK ,got any links on that?