Discussion Apple Silicon SoC thread

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Eug

Lifer
Mar 11, 2000
23,825
1,396
126
M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:

Screen-Shot-2021-10-18-at-1.20.47-PM.jpg

M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:


M1 Ultra discussion here:


M2 discussion here:


Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:


M4 Family discussion here:

 
Last edited:

Doug S

Platinum Member
Feb 8, 2020
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Also the CPU. From M1->M3 generation, the CPU has stuck to a 4P+4E configuration.

I have a feeling that M4 or M5, will upgrade that to 6P+4E or 4P+6E.

Why? Base models are base models. Apple doesn't offer hundreds of SKUs like Intel/AMD, so they want to maintain reasonable separation between each step in their lineup. It is more likely Apple will devote any additional area to a larger NPU or GPU.

There is already plenty of CPU power in the base Apple Silicon CPUs, the only reason to have more is for pointless pissing contests like Cinebench. If they bump that up too not only do they make their chip larger/more expensive, they have to bump up Pro and by extension Max to maintain useful separation between the product families.
 

Doug S

Platinum Member
Feb 8, 2020
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Maybe we will see more P cores in the base modell when Apple changes the P cluster size from 6 to 8 P cores on N2.

I think the driver of cluster size is more likely to be L2 cache contention. It probably doesn't have much to do with transistor density aside from an ability to make L2 larger if the process allows smaller SRAM cells - though that's a balancing act since a larger cache (and higher clock rate) implies higher latency.
 

Henry swagger

Senior member
Feb 9, 2022
504
306
106
I found this Chinese analysis of the A17 Pro, which is pretty dang impressive. In the video, he analyses the die area and was able to directly measure the density of the parts of the chip via electron microscope.
Beautiful scientific breakdown.. i.m sure tsmc will make him take down the video. Exposing all they secrets lol
 

SiliconFly

Golden Member
Mar 10, 2023
1,541
897
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Beautiful scientific breakdown.. i.m sure tsmc will make him take down the video. Exposing all they secrets lol
Not necessary for TSMC to take it down. Apple A17 Pro density was already known. This video revises it down by just 5%. No biggie. Also, the estimated (theoretical) peak density of TSMC N3 has already been estimated long back (~200), which tracks well with this. So, nothing to worry.
 

Henry swagger

Senior member
Feb 9, 2022
504
306
106
Not necessary for TSMC to take it down. Apple A17 Pro density was already known. This video revises it down by just 5%. No biggie. Also, the estimated (theoretical) peak density of TSMC N3 has already been estimated long back (~200), which tracks well with this. So, nothing to worry.
Still companies want to save face if they lied about density values
 

FlameTail

Diamond Member
Dec 15, 2021
3,950
2,376
106
I think the driver of cluster size is more likely to be L2 cache contention. It probably doesn't have much to do with transistor density aside from an ability to make L2 larger if the process allows smaller SRAM cells - though that's a balancing act since a larger cache (and higher clock rate) implies higher latency.
There are 2 ways to increase L2 size:

(1) Increasing the amount of L2 within a cluster, while keeping core count per cluster constant
+ L2 per core, is increased
+ Improves ST performance
+ Improves MT performance
- Increases die size

(2) Increasing the amount of L2, by increasing the core count per cluster, by the same factor
- L2 per core, is constant.
+ Improves ST performance
- MT performance is unchanged/regresses
+ Same die area
 

Doug S

Platinum Member
Feb 8, 2020
2,784
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@Doug S

You said N3B doesn't have FinFlex?

I am pretty sure TSMC claimed at one point that N3B did not include Finflex, but assuming that guy's analysis is correct it is used on A17P. I was confused though by his tables always showing N3E, not N3B, despite looking at A17P.

So I guess one of two things happened. Either my recall is incorrect and N3B always included FinFlex, or Apple got a slightly modified version of N3B. Apple is TSMC's largest customer and works closely with them on process development, and the official "start of mass production" for N3B was months in advance of when Apple's first wafers would be run. They are slotting BSPDN into N2 six months after its start of mass production, so it is at least possible the same was true with FinFlex and N3B for Apple.

I'll note the same gap between start of mass production and start of mass production for Apple's wafers also exists with N3E, so the possibility exists some elements of N3P could find their way into A18/M4.
 

FlameTail

Diamond Member
Dec 15, 2021
3,950
2,376
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I am pretty sure TSMC claimed at one point that N3B did not include Finflex, but assuming that guy's analysis is correct it is used on A17P. I was confused though by his tables always showing N3E, not N3B, despite looking at A17P.
He said that he was too lazy to change it from N3E to N3B, in the comments section of the video.
 

ashFTW

Senior member
Sep 21, 2020
312
235
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I am sure this are only for Apple servers. They probably don’t want to depend on Nvidia.
The AI custom silicon perhaps could also be used on the studio/pro in a multi-chiplet configuration. Depends if there is a unifying architecture behind this effort across the product stack.
 

Saylick

Diamond Member
Sep 10, 2012
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ashFTW

Senior member
Sep 21, 2020
312
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I'm sure it will be based on an upscaled version of their own iPhone NPU, right? Or rather, the NPU in the iPhone will be a scaled down version of the server chip.
Yes, but I assume it won’t purely be a tensor processor. The NPU on the current A&M chips exist along with CPU and GPU. Some of that type of processing will be required as well. And I/O.
 

poke01

Platinum Member
Mar 8, 2022
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The AI custom silicon perhaps could also be used on the studio/pro in a multi-chiplet configuration. Depends if there is a unifying architecture behind this effort across the product stack.
This is likely. Apple never designs for one config only but for it to scalable as possible.
 

Doug S

Platinum Member
Feb 8, 2020
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I am sure this are only for Apple servers. They probably don’t want to depend on Nvidia.

I'll believe it when I see it. There are always rumors about Apple doing servers, it never happens.

What does Apple need with a huge AI cloud when their whole thing is on device AI? They certainly aren't going to be competing with Nvidia selling stuff into the open market.

This is just some random Weibo user who has one accurate call in his past (I don't count "iPhone 7 will be waterproof" everyone was expecting that, he might as well count predicting Apple adopting 5G to juice his total)