Discussion Apple Silicon M series thread

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Eug

Lifer
Mar 11, 2000
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So good idea to pick up an M1 while it's still available.
Personally if I were in the market, I'd go for the fanless M2 MacBook Air.
Even if the M2 MBA throttles, it would not be much slower than the M1 MBP.
Or, if I really needed the performance, I'd get an M1 Pro MacBook Pro.

The 13" MacBook Pro is a very weird Apple product in 2022.
 
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Doug S

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We know that the Avalanche performance cores in both the M2 and A15 Bionic are clocked just over 8% higher than the corresponding Firestorm cores in the M1 and A14 Bionic, so that's already beyond just process improvements.

Not necessarily.

Yes, there would have been some tweaks to clean up a few critical paths etc. as is always the case with an iterative design, but it seems reasonable Apple can gain more than N5P's stated performance improvement because of the way they bin (or rather because they don't bin)

Apple selects a single target frequency which substantially all chips must reach. In statistical terms, they must select a frequency two standard deviations below the mean to reject only 2.5% of otherwise working dies as unable to meet frequency targets. There's no way of knowing what threshold they use, but it has to be in the two standard deviation ballpark to avoid tossing too many good dies.

It is reasonable to assume that when M1 Macs were introduced less than six months after N5 began mass production, the standard deviation of operating frequency would be larger than for N5P, introduced in M2 Macs about a year after starting mass production and two years after the N5 family began mass production.

For every MHz the standard deviation was reduced by TSMC's improved manufacturing consistency for M2 wafers vs M1 wafers, Apple's target frequency would be raised by 2 MHz if they used a two standard deviation threshold.
 

repoman27

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Dec 17, 2018
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Not necessarily.

Yes, there would have been some tweaks to clean up a few critical paths etc. as is always the case with an iterative design, but it seems reasonable Apple can gain more than N5P's stated performance improvement because of the way they bin (or rather because they don't bin)

Apple selects a single target frequency which substantially all chips must reach. In statistical terms, they must select a frequency two standard deviations below the mean to reject only 2.5% of otherwise working dies as unable to meet frequency targets. There's no way of knowing what threshold they use, but it has to be in the two standard deviation ballpark to avoid tossing too many good dies.

It is reasonable to assume that when M1 Macs were introduced less than six months after N5 began mass production, the standard deviation of operating frequency would be larger than for N5P, introduced in M2 Macs about a year after starting mass production and two years after the N5 family began mass production.

For every MHz the standard deviation was reduced by TSMC's improved manufacturing consistency for M2 wafers vs M1 wafers, Apple's target frequency would be raised by 2 MHz if they used a two standard deviation threshold.
The A15 was the lead product on N5P and the performance cores were clocked 8.07% higher than those in the A14. The performance gains claimed by foundries are generally absolute best case scenarios where they carefully select a point on the curve that allows them to tout the biggest numbers. Avalanche is 12.89% faster than Firestorm *and* uses 13.87% less power. This is not even close to the 4.35% clock speed increase *or* 14.29% power reduction claims by TSMC for N5P process improvement over N5. TSMC has never revised those numbers upwards because they are not tied to defect densities or parametric yields.

You really think Apple could have increased clocks by an additional 86% above and beyond what TSMC suggested was possible while also reducing power by 97% of their claimed maximum just through binning?
 

Doug S

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Don't think of it as "Apple gains more than N5P allows" think of it as "as first out of the gate with N5 Apple had to accept a lower frequency target than a fully mature N5 would have allowed".

If you look at the yield curve graphs (sorry can't remember where they were shown or I'd link them) N5 started lower (and went mass production at a lower yield) than N5P did in both cases.

When you are first to use a brand new process you have to make some frequency compromises when you don't bin.
 

soresu

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Dec 19, 2014
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M1 MacBook Pro vs M2 MacBook Pro:


Summary: M2 a bit faster for CPU, a lot faster for GPU, but M2 MBP fan runs more. The M2 fan noise is often much more noticeable than M1.
Not a great surprise IMHO - those laptops are hella thin for sustained use which is probably the main difference in performance vs M1 which seems to be very throttle heavy.
 

repoman27

Senior member
Dec 17, 2018
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Does anyone smell a product recall?
No, but I do smell typical click-bait YouTube channel nonsense.

Everything we know about the microarchitecture of the M2 as compared to the M1 is that it is both faster and significantly *more* efficient. It uses less power to complete the same task in less time. Just look at the battery life difference between the iPhones 12 and 13. Why should we expect a different outcome for the M2? AFAWK, nothing changed about the chassis or thermal design of the 13-inch MacBook Pro. Apple's battery life and capacity claims are the same for both models.

Vadim's first photo shows a temp of 108ºC/93ºC (who knows which sensors that data is coming from) and a fan speed of 1200 RPM. Then he claims that the fans were pegged at 7200 RPM the whole time. Maybe he did see the reported behavior, who knows, but the conclusion he arrives at is rubbish.

I'm sure Apple will push out a firmware fix if there is an actual issue. But there's obviously nothing inadequate about the cooling system in the 13-inch MacBook Pro.
 
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repoman27

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There has been rumors that the M2 Pro & M2 Max chips will be on 3nm. It might be true after all.
Oh, you mean those rumors that are also being widely promoted by the same individual (Vadim Yuryev)? Because those rumors also strike me as utter nonsense coming from people who have no idea what they're talking about.
 

richardskrad

Junior Member
Jun 28, 2022
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You are correct. I skimmed through his Tweets and it seems like he's blowing things out of proportion to drive traffic to their YouTube channel. This creator might be the biggest user of clickbait I've seen in a while.

 
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Ajay

Lifer
Jan 8, 2001
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The Pro die isn't really all that big (and is binned on cores to increase yield) and while the Max die is fairly large (but also binned) they don't need a whole lot of those and the Macs they go in sell at pretty fat margins.

Heck, N3 risk production is well underway by now, and TSMC said they'd be running 30K wpm during risk production. That seems pretty high, unless there will be actual customer wafers getting made alongside the test shuttles at some point in the risk production cycle. If Apple wanted to be aggressive they could ship M3 Pro/Max Macs before the first official mass production wafers were complete.

Anyway this is all rather pointless speculation based on rumors which in turn are based on more rumors. At some point the bulls--- starts piling up so much you need to open a few windows :)
I got kind of excited about this at first because, as your point out, the volume Apple needs isn't that high - at least to begin with. But then, IIRC, A16 is supposed to be on N4, so, bollocks. It would be cool if the M2 Pro and Max were on N4, a bit higher clock with the likely improvements of the A16 cores would make for a nice step up. Of course, rumors are fun, to an extent and until they get smashed by reality.
 

repoman27

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Dec 17, 2018
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Don't think of it as "Apple gains more than N5P allows" think of it as "as first out of the gate with N5 Apple had to accept a lower frequency target than a fully mature N5 would have allowed".

If you look at the yield curve graphs (sorry can't remember where they were shown or I'd link them) N5 started lower (and went mass production at a lower yield) than N5P did in both cases.

When you are first to use a brand new process you have to make some frequency compromises when you don't bin.
I can see the point you're trying to make here, but I think you may not be remembering correctly what those graphs look like.

First there's the N5 yields:



So by the time N5 hit HVM in Q2'20 and Apple ramped the A14, D0 was already insanely low and the yield curve was essentially flat.

Then there's N5P vs N5 performance. Performance claims coming from foundries for newly launched processes are generally based on simple test structures, which are usually something like a ring oscillator with some fan-outs. Defect density has little bearing on the oscillation time and effective drive current of those types of structures, meaning that the performance claims are more closely tied to properties intrinsic to the process itself. They are also generally quite optimistic and rarely correlate well to the actual performance gains seen for a decently sized SoC. Here's a plot for an SoC on N7P vs N7, which offered ">5%" performance increase at the same power, or slightly better that N5P vs N5:



Note that the slope of the two lines is very similar, which we would expect seeing as N7P is part of the N7 process family, uses the same design rules, and is really just N7 with a year's worth of minor improvements. The same should hold true for N5P vs N5.

And finally, here's a plot comparing TSMC N7 and Samsung 10LPP based on Qualcomm's Snapdragon 855, showing a 10% speed improvement at 35% lower power:



Now imagine that plot adjusted slightly to show a 13% speed improvement at 14% lower power, just move the red line to the right a click and raise it up a couple. That's what A15 on N5P would look like in relation to A14 on N5.

edit: Also, Apple does bin, but I believe they typically do so based on leakage/power rather than frequency. Every chip that goes in a product is capable of hitting the target frequency, but how much power it uses to get there determines which product it goes in (e.g. iPhone mini, iPhone, iPhone Pro, iPhone Pro Max, iPad mini, iPad, Apple TV, Studio Display)

BTW, the latter graphs were pulled from this WikiChip article, which is a good read in general, but the second page seems particularly relevant to this discussion.
 
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Doug S

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I got kind of excited about this at first because, as your point out, the volume Apple needs isn't that high - at least to begin with. But then, IIRC, A16 is supposed to be on N4, so, bollocks. It would be cool if the M2 Pro and Max were on N4, a bit higher clock with the likely improvements of the A16 cores would make for a nice step up. Of course, rumors are fun, to an extent and until they get smashed by reality.

The reason I suggested that is because we have another rumor - that A16 will be only in the Pro lineup and not in the non-Pro iPhone 14.

Why would Apple do that? It is hard to argue they are doing it to give more reasons for people to pay more for the Pro - they've never had difficulty doing that when they have the same CPU. That idea really falls apart though when you consider the low end (for Apple) iPhone SE will have been on the market for 6 months with the same A15 that would go in the non-Pro iPhone 14.

The only reason I can think of why they'd limit A16 to the Pro phones is 1) quantity of A16s is limited or 2) A16s are more expensive - and not just a few dollars more expensive. N4 should be less expensive per wafer, but certainly won't be more expensive.

So either A16 is on a process that's limited (not a problem for N4) or is significantly larger than A15. If it is limited in quantity, then maybe Apple found a way to make on them on risk production N3 wafers. Unlikely, but not totally impossible. If it is more expensive, maybe it was originally intended for N3 but when making it on N3 become impossible it was backported to N4 - making it larger and therefore more expensive than any recent iPhone SoC.

Either or both rumors could be totally wrong, but if there is something true in both rumors I think it is likely they are true for related reasons.
 
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repoman27

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The reason I suggested that is because we have another rumor - that A16 will be only in the Pro lineup and not in the non-Pro iPhone 14.

Why would Apple do that? It is hard to argue they are doing it to give more reasons for people to pay more for the Pro - they've never had difficulty doing that when they have the same CPU. That idea really falls apart though when you consider the low end (for Apple) iPhone SE will have been on the market for 6 months with the same A15 that would go in the non-Pro iPhone 14.
Yeah, that rumor is a head-scratcher. So Apple is going to release a total of 7 different iPhone models based on the same SoC? The A13 and A14, the previous record holders, only had 4 apiece... Seems suspect.

The only reason I can think of why they'd limit A16 to the Pro phones is 1) quantity of A16s is limited or 2) A16s are more expensive - and not just a few dollars more expensive. N4 should be less expensive per wafer, but certainly won't be more expensive.

So either A16 is on a process that's limited (not a problem for N4) or is significantly larger than A15. If it is limited in quantity, then maybe Apple found a way to make on them on risk production N3 wafers. Unlikely, but not totally impossible. If it is more expensive, maybe it was originally intended for N3 but when making it on N3 become impossible it was backported to N4 - making it larger and therefore more expensive than any recent iPhone SoC.
N4 offers a 6% optical shrink, performance and yields similar to N5P, and possibly some reduction in complexity / cost. I highly doubt Apple would intentionally design an SoC that went and blew the area budget in such a way that it couldn't be used across the product line. The only way I can see there being a major cost difference or supply constraint with the A16 would be if it employed some crazy new packaging technology. Or it includes an integrated 5G modem a year before anyone expected it to and despite the rumors claiming Apple's work on their own 5G modem has "failed".

The most plausible way I can reconcile the rumors is that there are other supply chain constraints at work here. Like maybe the A16 uses LPDDR5 and Apple can't source enough without causing undue supply / price pressure, so they need to keep a significant number of devices on LPDDR4X for another year.

It really isn't possible to use risk starts on a new process node prior to HVM to manufacture a 90+ mm² SoC destined for consumer products. Glance back up at that defect density chart for a minute and note where D0 is at in the quarters prior to the MP point. The iPhones Pro alone would still make this one of the highest volume SoCs being produced on a leading node, and they are still extremely cost sensitive parts even if they are going into what are considered expensive phones. All of the customers who booked N3 wafer starts will need to do some degree of risk production. That's their chance to discover problems and work with TSMC to resolve issues in order to get the process to the point where HVM can actually begin. Using early risk starts for an A series chip is not possible from a cost perspective, a volume perspective, or a timing perspective.

Likewise, the idea that the M2 Pro and M2 Max would be made on N3 is pretty much right out. They will almost certainly be based on the same microarchitectures as the A15 and M2, and most likely manufactured on N5P. However, Apple may well have taped them out for N4 instead given the timing and the fact that N4 is pretty much N5P with a slight shrink. It is also possible that Apple could make the M3 their lead product on N3 with the first products being announced as early as June 2023. That actually makes some degree of sense.
 
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Doug S

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The most plausible way I can reconcile the rumors is that there are other supply chain constraints at work here. Like maybe the A16 uses LPDDR5 and Apple can't source enough without causing undue supply / price pressure, so they need to keep a significant number of devices on LPDDR4X for another year.

That's possible though LPDDR5 has been used on Android phones for a couple years now. Hard to imagine supply could be an issue when LPDDR5X phones will be launching soon if they haven't already. I have no idea about the cost, anyone have any idea of LPDDR5 vs LPDDR4X pricing for 4GB?

Using different SoCs simply because they want to use LPDDR5 on Pro and LPDDR4X on non Pro seems a bit odd to me. It isn't as though they couldn't do a second version of A16 with LPDDR4X controllers - they already sorta did that with M1, which had LPDDR4X controllers while M1 Pro/Max got LPDDR5 controllers. Since LPDDR4X controllers take less space they don't need to change anything else just swap in the new controllers and leave some empty space on the die. They did two versions of A8, shipping last year's SoC because they want to save money on a second mask set seems pretty penny pinching. We're talking maybe an extra 25 cents per non-Pro iPhone.


It really isn't possible to use risk starts on a new process node prior to HVM to manufacture a 90+ mm² SoC destined for consumer products. Glance back up at that defect density chart for a minute and note where D0 is at in the quarters prior to the MP point. The iPhones Pro alone would still make this one of the highest volume SoCs being produced on a leading node, and they are still extremely cost sensitive parts even if they are going into what are considered expensive phones. All of the customers who booked N3 wafer starts will need to do some degree of risk production. That's their chance to discover problems and work with TSMC to resolve issues in order to get the process to the point where HVM can actually begin. Using early risk starts for an A series chip is not possible from a cost perspective, a volume perspective, or a timing perspective.

TSMC previously said they'd be making 30K wpm in N3 risk production. That seems like a lot. Maybe it is because they have a lot of customers, or maybe it is because one of the customers is going to actually use a bunch of them to make a sufficient number of chips despite a low yield. Yeah I don't really buy it either, but it is not completely impossible.


Likewise, the idea that the M2 Pro and M2 Max would be made on N3 is pretty much right out. They will almost certainly be based on the same microarchitectures as the A15 and M2, and most likely manufactured on N5P. However, Apple may well have taped them out for N4 instead given the timing and the fact that N4 is pretty much N5P with a slight shrink. It is also possible that Apple could make the M3 their lead product on N3 with the first products being announced as early as June 2023. That actually makes some degree of sense.

I agree the idea that M2 Pro/Max will be made on N3 is right out. But I disagree that it is right out skipping M2 Pro/Max entirely and shipping Macs with M3 Pro/Max using A16 cores made on N3 early next year.

There has to be someone using all the N3 wafers that will enter mass production in the next few months, and ship for revenue in early 2023. That's all Apple could use them for until this time next year. They can't be one of the "lead customers" if they don't take any wafers until six months after mass production shipments have begun!

That "lead customer" thing is the one real mystery here. How can Apple be a lead customer for N3 if N3 wafers are shipping for half a year without any going to Apple? SOMETHING is going to get made on N3 prior to next summer, or that "lead customer" thing was a lie.
 

repoman27

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That's possible though LPDDR5 has been used on Android phones for a couple years now. Hard to imagine supply could be an issue when LPDDR5X phones will be launching soon if they haven't already. I have no idea about the cost, anyone have any idea of LPDDR5 vs LPDDR4X pricing for 4GB?
There are plenty of devices using LPDDR5, that isn't the point. Apple purchases a significant percentage of the global output of DRAM each year. The A series SoCs are so insanely high volume that changing memory technologies can only happen once the suppliers are capable of meeting that kind of demand.

This is the classic reason why Android devices often showcase certain technologies before the iPhone gets them. Suppliers can't just scale up component production several orders of magnitude overnight.

TSMC previously said they'd be making 30K wpm in N3 risk production. That seems like a lot. Maybe it is because they have a lot of customers, or maybe it is because one of the customers is going to actually use a bunch of them to make a sufficient number of chips despite a low yield. Yeah I don't really buy it either, but it is not completely impossible.
Did TSMC ever say that? Pretty sure it was actually Digitimes.

It would be completely unprecedented to manufacture an SoC for a high-volume consumer product using pre-production risk starts. The iPhones Pro alone would require at least 75,000 wafer starts over the course of Q2-Q3 2022, or potentially more than 40% of the total starts during that period. It would also cost Apple at least $150 million dollars more than simply waiting until the process was ready for zero discernible difference to the customer. In other words, pure waste. This is the antithesis of how Apple operates.

I agree the idea that M2 Pro/Max will be made on N3 is right out. But I disagree that it is right out skipping M2 Pro/Max entirely and shipping Macs with M3 Pro/Max using A16 cores made on N3 early next year.

There has to be someone using all the N3 wafers that will enter mass production in the next few months, and ship for revenue in early 2023. That's all Apple could use them for until this time next year. They can't be one of the "lead customers" if they don't take any wafers until six months after mass production shipments have begun!

That "lead customer" thing is the one real mystery here. How can Apple be a lead customer for N3 if N3 wafers are shipping for half a year without any going to Apple? SOMETHING is going to get made on N3 prior to next summer, or that "lead customer" thing was a lie.
Once again, who said Apple was a lead customer for N3? (I mean, it pretty much goes without saying that they probably are, but...)

TSMC said to expect commercial N3 wafer outs starting in Q1'23. HVM is likely beginning in Q4'22, and cycle times are probably around 100 days. There's a long road between getting finished wafers back from the foundry and putting a completed device into end users' hands. Intel is also rumored to be one of the first to use N3 and nobody is expecting Meteor Lake before Q2'23. That's why I said June, because it's not possible to do a quicker turn-around than that for something like the MacBook Air. And who knows, the S8 or H2 might end up being Apple's first chip on N3.

The M2 Pro and M2 Max actually exist though. Mark Gurman may be a leaker, but he has also acquitted himself as a legitimate journalist and currently handles the Apple beat for Bloomberg (for whatever that's worth). He has posted several pieces over the past few months citing specific product codenames gleaned from the telemetry logging of third-party apps. This is pretty clear evidence that these products are already undergoing testing at Apple and far enough along in the process that employees are running third-party apps and connecting to the internet with them.

A quick recap of the products he enumerated:

Device CodenameDeviceSoCSoC Codename*
J617iPad Pro, 11-inch (4th generation)M2Staten
J620iPad Pro, 12.9-inch (6th generation)M2Staten
J374Mac miniM1 ProJade Chop
J473Mac miniM2Staten
J474Mac miniM2 ProRhodes Chop
J414MacBook Pro (14-inch)M2 ProRhodes Chop
J414MacBook Pro (14-inch)M2 MaxRhodes 1C
J416MacBook Pro (16-inch)M2 ProRhodes Chop
J416MacBook Pro (16-inch)M2 MaxRhodes 1C
J180Mac ProM2 UltraRhodes 2C
J513MacBook Air (13-inch)M3Ibiza
J515MacBook Air (15-inch)M3Ibiza
J433iMac (24-inch?)M3Ibiza
*some SoC codenames were provided by sources other than Gurman

Gurman also specifically mentioned a MacBook Pro (14-inch) that reported an M2 Max with 12 CPU cores, 38 GPU cores, and 64GB of unified memory.

As far as SoC codenames go, the M3 family apparently includes Ibiza, Lobos, and Palma, but no chops or multi-die variants have been cited yet.
 
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richardskrad

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Your posts must include your own original written content in the CPUs forum.

AT Moderator ElFenix
 
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igor_kavinski

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1657215221042.png

M2 not really optimized for Handbrake.

1657215167809.png

But M2 battery life is amazing.

1657215395310.png

M2 losing to a relatively cheaper Tiger Lake i5 with Geforce 3050.
 

Doug S

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M1 had the same problem.

Is it Apple Silicon that is not optimized for Handbrake, or Handbrake that is not optimized for Apple Silicon?

There is a lot of software that is only optimized for x86, and for Mac basically gets "it compiled without errors and seems to run, ship it!" treatment.
 
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