Anyone know about simple multi-cycle CPU design?

[duragezic]

Alright maybe no one can really help me on this so I'll try to keep it general.

We need to design (use a circuit/logic simulation program from our school) a multi-cycle CPU. It's very close to a MIPS implementation, except that words are 16 bits instead of 32 bits.

So it's based off the the multi-cycle CPUs in the Henessey and Patterson book.

Now, the requirement for this CPU which is totally killing me is the memory access time must be 2000 (doesn't matter units). With the default access time of 200, my CPU works fine for the instructions I've done so far (add, sub, lw, sw, beq, bne). But changing it to the required 2000 totally messes things up.

Since the memory takes about a whole cycle to just read it, the rest of my states (multi cycle CPU control signals are implemented with a state machine) get messed up. We can add delay elements, but I have no clue where. Basicaly the states are:

fetch instruction, so it reads the program counter's default address of 0, but the instruction/data memory requires an access time of 2000. My cycle time is 2000 (I've experimented up to 3500, but I know 2000 is a rough start).

decode instruction: here it assumes the memory has read out the instruction and then procedes to load it into the instruction register and decode what registers and operation to perform. The problem is that it gets to this state before the memory has read the instruction, so it decodes 0000, which is interepted as a HALT instruction, thus stops.

Anyone have any ideas on how I can choose a cycle time and one time? I have no idea how to determine the one time (the time the clock is high). My registers are all negative-edge triggered, but I've tried some of them as positive or level, but stil it doesn't work.

 

[helpme]

I'm not sure if I understand your problem right. Are you saying that your memory takes 2000 time units to complete an operation, while the rest of the ops take at most 200 units?

If the basic unit access time is 200units, can't you make the fetch instruction take 10 states? That way you'll have used 2000 time units by the time you move to the next step.

 

[duragezic]

Not quite... the memory does take 2000 time units to access it. Each state requires one cycle. Every instruction/operation has the first two states in common (fetch instruction and update PC for next instr, then decode that 1st instruction), and then for example, subtraction has two more states following the two common to all instructions. So for subtraction it would require a little over 4 states *2000 cycle time + a little extra for gates and register propagation delays. Currently I have the cycle time set to 2000, and the time it is high (one time) set to 200. But I have a hard time determining what values to set these to. Because my registers don't trigger at the right time correctly since the clock is not falling at the right time. My instruction register doesn't ever take in the instruction because it doesn't have a falling edge of the clock to trigger, thus it tries to decode the default value in the instruction register of 0.

I did try making the states go:

fetch -> nop -> decode -> rest of states depending on op code

So that fetch would take 2000 time, nop another 2000, then by 4000 it would start to decode, since the memory requires 2000 time to access. But that doesn't quite do it either.

Damn, I guess this is hard to explain.. I figured it'd be tough for anyone to help, but thought maybe someone who has done this type of class before could clue me in on how to choose a cycle time and one time. Because, it doesn't matter if my CPU is slow (hell it's gonna be slower than my one-cycle design, which shouldn't be) as long as it works.

 

[neutralizer]

Computer Organization and Design, that book? I took the class for that but totally forgot how to do it. Probably would have been better ingrained in my head if Patterson himself taught the class.

 

[IceBergSLiM]

this is off topic we have other forums for this.

 

[helpme]

I'm not quite sure if I understand your problem still. I'm not sure what you mean by "one time" in relationship to your cycle time. Don't you have a duty cycle of 50%, giving you a 2000 time unit clock, with 1000 time units high? The data should flow between registers as long as no group of combinational logic takes more than the 2000 time units to process.

Do you have a schematic that we could look at?

I actually used that same book when I was in school, great book, and did a simlar project. Shoot me a PM and maybe we can work through it offline, it shouldn't be too hard to solve.