I am an EE major and was just contacted by Intel yesterday requesting a 1hr. technical phone interview for tomorrow. The interview will cover circuit design, logic design, and some CS, but they would not be more specific because they don't want people to study for them. Has anyone had a technical phone interview with Intel before? How difficult are they, and what types of questions did they ask you?
Anyone here ever have a phone interview with Intel?
- Thread starter Special K
- Start date
OK so I had the interview today. Overall it went fairly well. I knew the answers to most of the questions. A few I partially knew the answer to, or got it all after the guy gave me some hints, but there were a couple hard ones that he totally stumped me on. Do I have to ace the technical phone interview to have a shot at a job? I know there are a few people here who work at Intel, if you read this could you post your experience/advice?
thanks
thanks
Einz
Diamond Member
- May 2, 2001
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up for not being loved!
really though, i'm not EE so i've never had a intel interview before. i've had phone interviews where the interviewer asked a question that stumped me, but it turned out well in the end; they requested an in person interview. best of luck to ya
really though, i'm not EE so i've never had a intel interview before. i've had phone interviews where the interviewer asked a question that stumped me, but it turned out well in the end; they requested an in person interview. best of luck to ya
DT4K
Diamond Member
- Jan 21, 2002
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I had a phone interview, but it wasn't technical. They asked me some general questions, then offered to fly me to their Oregon or Arizona locations for a college recruiting event and in person interviews. This was for software development, not engineering. The in person interview was pretty normal, but they did throw in some of those bizarre problem solving questions that places like Microsoft are known for. I don't know how well I did because 2 weeks later, they called and told me they had a hiring freeze and weren't making offers to anyone. This was June, 2001.
I haven't had one with intel but I am a working EE.
I think the phone interview sets you up for a fly in interview if you do ok.
can you post some of the problems ?
I think the phone interview sets you up for a fly in interview if you do ok.
can you post some of the problems ?
I've had several phone interviews and technical interviews (although not with intel...xilinx, medtronic, maxtor). It's really not so much that you "ace" the technical part...what they are looking for is how you approach problem solving. They like you to talk out loud in order to see your thought process. If you sit idle and don't say anything and then say, "i give up", then they think that you have no clue what you're doing, even if you have been turning the cogs so to speak. so as long as you show how you solve problems and have good people skills, i'd say you have a pretty good chance.
I'm a senior in CPE/EE/CSC and had 3 phone interviews with Intel this year, 2 for a position in Portland and 1 for a position in Hudson. I felt like I knew maybe about 60-70% of the stuff they asked in the phone interviews. The Hudson location called me back to bring me up for onsite interviews, which surprised me because I thought I did pretty bad overall.
Anyways, after the onsite interviews (6 technical interviews straight through the day), I completely bombed most of the day, and was not offered the position. Hopefully you'll have more luck than I did... let me know if you want to hear about some of the questions asked during the onsite interviews. The position was in product engineering for network processors.
Anyways, after the onsite interviews (6 technical interviews straight through the day), I completely bombed most of the day, and was not offered the position. Hopefully you'll have more luck than I did... let me know if you want to hear about some of the questions asked during the onsite interviews. The position was in product engineering for network processors.
It depends on the site and position you were interviewing for ...it's not all about whether you can answers every single question but how you work through it. Just be prepare to get a full day of interviews if you get invited. good luck. BS or MS grad?
good luck. BS or MS grad?2 years ago, i had a phone interview with intel. this was when i was laid off from another company of the same nature. they offered me a position after all of the interviews and flying out to california and then to massachusetts. I would have been a EE. However, i turned them down because of my daughter is here in virginia and lives with her mother.
Intel is a great company. Very stable. However, in the semiconductor biz.... its always up in the air about whether they are going to close a plant here, or there. This biz is cyclicle. A few years good, a few years bad. Either way, if you can get in, and get plenty of time, and dont mind traveling to get ahead and make alot of money... i say do it if they offer you a position. If you want to know about bennies, there are a few intel employees on this board....
Intel is a great company. Very stable. However, in the semiconductor biz.... its always up in the air about whether they are going to close a plant here, or there. This biz is cyclicle. A few years good, a few years bad. Either way, if you can get in, and get plenty of time, and dont mind traveling to get ahead and make alot of money... i say do it if they offer you a position. If you want to know about bennies, there are a few intel employees on this board....
I will graduate this May with a BSEE. I have already applied to grad schools and my intent was to get a MSEE at a school that Intel recruits at, and then get a job with them from there. I really want to work for one of the big VLSI/microprocessor companies, but none of them recruit at my school, so I figured my only way of getting noticed by these places was to go to a school they recruit at for grad school. I applied to Intel via their website and suprisingly got an email about the possibility of a chipset design position in Folsom, so that's what they called me about yesterday.
EDIT: I was also considering the MSEE prior to working because I have read it generally commands a higher starting salary and companies will give you better projects to work on, but I can't verify that.
The questions they asked me during the interview included:
What is the difference between a latch and a flip flop?
What is a finite state machine, and what would they be used for?
How many flip flops would it take to encode a state machine with 7 states, using standard encoding?
What is the difference between SRAM and DRAM, and in what situations would you choose 1 instead of the other?
What is a pipeline, and what are the potential hazards that can arise from using one?
What is the difference between behavioral and structural VHDL?
What command in UNIX would you use to search for a particular string within a file?
Explain how a CMOS inverter works
Name and describe the 3 modes of operation of a transistor
They also asked me to simplify a logical function of 4 variables, and to derive the next state and output equations for a 2 state FSM. Questions I did not know the answer to included:
What is the primary advantage of using one hot encoding over standard encoding? (I knew what one hot encoding was, but not the advantages of it)
If you increase the supply voltage to a digital circuit, would you expect the circuit to run faster or slower, assuming the circuit can handle the increased voltage? (The correct answer is faster, because if you consider the IV characteristics of a transistor, higher values of Vgs have steeper IV curves and will reach saturation sooner than ones with a lower Vgs. It made sense after he explained it, but I just couldn't think of it at the time)
Here was the hardest one they asked me:
Suppose you have a D flip flop whose output passes through some combinational logic and then into the input of another D flip flop. Also suppose that this part of the circuit was not meeting its setup and hold time requirements. How would you correct this problem? (I really had no idea on this one. I suggested the obvious, which was reduce the clock rate and try to simplify the combinational logic to reduce the delay, but he was looking for something else. I mentioned clock skew and he asked me to elaborate on that, so I think I got some credit for answering the question. He never did tell me the correct answer to that one though.)
There were some of the others in the first list I struggled with a bit, but evenutally got the right answer. I think I missed the output to the state machine question too.
EDIT: I was also considering the MSEE prior to working because I have read it generally commands a higher starting salary and companies will give you better projects to work on, but I can't verify that.
The questions they asked me during the interview included:
What is the difference between a latch and a flip flop?
What is a finite state machine, and what would they be used for?
How many flip flops would it take to encode a state machine with 7 states, using standard encoding?
What is the difference between SRAM and DRAM, and in what situations would you choose 1 instead of the other?
What is a pipeline, and what are the potential hazards that can arise from using one?
What is the difference between behavioral and structural VHDL?
What command in UNIX would you use to search for a particular string within a file?
Explain how a CMOS inverter works
Name and describe the 3 modes of operation of a transistor
They also asked me to simplify a logical function of 4 variables, and to derive the next state and output equations for a 2 state FSM. Questions I did not know the answer to included:
What is the primary advantage of using one hot encoding over standard encoding? (I knew what one hot encoding was, but not the advantages of it)
If you increase the supply voltage to a digital circuit, would you expect the circuit to run faster or slower, assuming the circuit can handle the increased voltage? (The correct answer is faster, because if you consider the IV characteristics of a transistor, higher values of Vgs have steeper IV curves and will reach saturation sooner than ones with a lower Vgs. It made sense after he explained it, but I just couldn't think of it at the time)
Here was the hardest one they asked me:
Suppose you have a D flip flop whose output passes through some combinational logic and then into the input of another D flip flop. Also suppose that this part of the circuit was not meeting its setup and hold time requirements. How would you correct this problem? (I really had no idea on this one. I suggested the obvious, which was reduce the clock rate and try to simplify the combinational logic to reduce the delay, but he was looking for something else. I mentioned clock skew and he asked me to elaborate on that, so I think I got some credit for answering the question. He never did tell me the correct answer to that one though.)
There were some of the others in the first list I struggled with a bit, but evenutally got the right answer. I think I missed the output to the state machine question too.
wow, that is a lot for a phone interview.
But yeah standard array of VLSI questions.
to the ones which you didn't get.
The advantage of a 1 hot encoding is that there will be no conflicting voltage in the mux and there will be no high impedence Z state in which none of the select lines are on.
The last question is very common and is similar to a question I asked somebody recently.
Not meeting setup and hold meeting hold are two different things. Not meeting setup means the data is arriving at the flop too late and thus can not write in to the master latch of the flop.
Not meeting hold means that the flop is not able to hold the value previously stored. either violation can cause metastability (unknown 1 or zero stored) and what they call race conditions in which the data and clock are essentially racing to see who can get to the flop first.
Clock Skew refers to when there is a delay between when the clock arrives at flop 1 vs when the clock hits flop 2.
To fix setup and hold violations, you can redesign your flop, add buffers in to your clock tree. With a hold issue, reducing the delay in your combinational logic actually worsens the problem.
But yeah standard array of VLSI questions.
to the ones which you didn't get.
The advantage of a 1 hot encoding is that there will be no conflicting voltage in the mux and there will be no high impedence Z state in which none of the select lines are on.
The last question is very common and is similar to a question I asked somebody recently.
Not meeting setup and hold meeting hold are two different things. Not meeting setup means the data is arriving at the flop too late and thus can not write in to the master latch of the flop.
Not meeting hold means that the flop is not able to hold the value previously stored. either violation can cause metastability (unknown 1 or zero stored) and what they call race conditions in which the data and clock are essentially racing to see who can get to the flop first.
Clock Skew refers to when there is a delay between when the clock arrives at flop 1 vs when the clock hits flop 2.
To fix setup and hold violations, you can redesign your flop, add buffers in to your clock tree. With a hold issue, reducing the delay in your combinational logic actually worsens the problem.
as to the other questions
1. latch is single storage, flop is essentially 2 latches. latch is flow through AKA level sensitive flop is edge sensitive
2. Finite state machine used for any sequential logic
3. I believe 3
4. sram typically has a latch connected to a sense amplifier, dram is typically just a static capacitance and needs periodic refreshing due to charge leakage. You would use sram if you wanted to read/write fast (in your cache for example) , you use dram to save space.
5. pipeline is flop -> combinational -> flop -> combination -> flop -> combinational..... race conditions, metastability, extra overhead,
6. behaviour Verilog is behavior of the circuit such as c= a + b for an adder, structural is the gate level verilog
7. I belive grep
8. too long to type out here, learn the cmos inverter well, also learn the nand well, common interview questions arise from variations on these.
9. linear, saturation, and I forget the technical word for off.
1. latch is single storage, flop is essentially 2 latches. latch is flow through AKA level sensitive flop is edge sensitive
2. Finite state machine used for any sequential logic
3. I believe 3
4. sram typically has a latch connected to a sense amplifier, dram is typically just a static capacitance and needs periodic refreshing due to charge leakage. You would use sram if you wanted to read/write fast (in your cache for example) , you use dram to save space.
5. pipeline is flop -> combinational -> flop -> combination -> flop -> combinational..... race conditions, metastability, extra overhead,
6. behaviour Verilog is behavior of the circuit such as c= a + b for an adder, structural is the gate level verilog
7. I belive grep
8. too long to type out here, learn the cmos inverter well, also learn the nand well, common interview questions arise from variations on these.
9. linear, saturation, and I forget the technical word for off.
My phone interview was similar. No Unix questions as I recall, but I had the latch/flip-flop - and they followed it up with a question about transparency. It was 10 years ago though.
I got the setup one too - the hard one. Made me smile to see you got it too. I actually ask it to people now. In hindsight, I struggled, my interviewer gave hints and I finally got it right. The answer that she was looking for was to change the clock tree - which was something that I hadn't thought of right away.
After the first phone call, I got phone interviewed a second time by someone on the team that was looking at hiring me. The second was far more difficult (I remember he had me draw a circuit with at least 8 FETs in it over the phone. ) and lasted quite a bit longer. At the end up of that, he said that I should come down for an interview and gave me some numbers of the Intel travel office to call to set it up.
Then I went down, spent the night in the Biltmore across the street and then we had a really long day of interviews. Four interviews lasting 45 minutes each, with a 15 minute break, for 4 rounds: circuit design, logic design, architectural/programming, and then test & manufacturing. I did great in 2 of them, bombed one of them (architectural) and then did ok in logic design. In the afternoon, we had a tour of the campus. Then in the evening, we had dinner with the teams that were looking at hiring us. They said it wasn't an interview... but it was.
I received an offer about 4 days later.
I've been working for Intel for 10 years now - started designing Pentiums (P54CS... the 133/166/200MHz Pentium), and then have been working on Itanium design ever since. I really like Intel and honestly wouldn't consider working anywhere else unless the salary difference was ridiculous.
Good luck, and if you want to emai/IM/phone talk about anything, SpecialK, just email and I can give you my IM, and/or phone number. My site isn't hiring, but I'm sure that could answer any questions that you might have.
I got the setup one too - the hard one. Made me smile to see you got it too. I actually ask it to people now. In hindsight, I struggled, my interviewer gave hints and I finally got it right. The answer that she was looking for was to change the clock tree - which was something that I hadn't thought of right away.
After the first phone call, I got phone interviewed a second time by someone on the team that was looking at hiring me. The second was far more difficult (I remember he had me draw a circuit with at least 8 FETs in it over the phone.
) and lasted quite a bit longer. At the end up of that, he said that I should come down for an interview and gave me some numbers of the Intel travel office to call to set it up.Then I went down, spent the night in the Biltmore across the street and then we had a really long day of interviews. Four interviews lasting 45 minutes each, with a 15 minute break, for 4 rounds: circuit design, logic design, architectural/programming, and then test & manufacturing. I did great in 2 of them, bombed one of them (architectural) and then did ok in logic design. In the afternoon, we had a tour of the campus. Then in the evening, we had dinner with the teams that were looking at hiring us. They said it wasn't an interview... but it was.
I received an offer about 4 days later.
I've been working for Intel for 10 years now - started designing Pentiums (P54CS... the 133/166/200MHz Pentium), and then have been working on Itanium design ever since. I really like Intel and honestly wouldn't consider working anywhere else unless the salary difference was ridiculous.
Good luck, and if you want to emai/IM/phone talk about anything, SpecialK, just email and I can give you my IM, and/or phone number. My site isn't hiring, but I'm sure that could answer any questions that you might have.
Thanks for the info pm! As it turns out I was notified today that they will fly me out for an interview at their site in Folsom CA on 2/18.
Congrats :thumbsup:
I know some guys that work for Intel in Folsom. It's about 20 miles from here.
grats dude. hopefully the weather will stay nice like it is today.. its beein real sh!tty lately. good luck!!
<-- Works at Intel as a Photolithography Fab Technician, a notch (or two or three) lower on the technical scale than an EE such as pm.
My phone interview was just over four years ago. It took about 30 mins. I missed a few questions, but I guess I did well enough that they invited me in for a full interview.
My onsite interview was significantly more difficult. It lasted most of the day, with the technical grilling taking up about three hours of that. I missed a few questions, but the fact that I was able to follow the interviewers lead and logically come to the correct conclusion was significantly more important. I remember not being all that excited when they told me I got the job... I was just mentally exhausted.
Intel is an excellent company to work for. Probably the most stable in the high tech industry and the benefits are very, very good. About the only way I don't see myself retiring here, is if I stumble into starting some incredibly successful business of my own.
My phone interview was just over four years ago. It took about 30 mins. I missed a few questions, but I guess I did well enough that they invited me in for a full interview.
My onsite interview was significantly more difficult. It lasted most of the day, with the technical grilling taking up about three hours of that. I missed a few questions, but the fact that I was able to follow the interviewers lead and logically come to the correct conclusion was significantly more important. I remember not being all that excited when they told me I got the job... I was just mentally exhausted.
Intel is an excellent company to work for. Probably the most stable in the high tech industry and the benefits are very, very good. About the only way I don't see myself retiring here, is if I stumble into starting some incredibly successful business of my own.
Those are some nice questions, along the lines of what I would ask.
It's always better to start with the really easy ones, because you would be surprised how many EE grads don't even know simple things like sizing combinational gates.
It's always better to start with the really easy ones, because you would be surprised how many EE grads don't even know simple things like sizing combinational gates.
UPDATE: I got an interview at the Folsom site, and also got a call from someone at the Austin site for a possible job with the IA-32 architecture group. I have a phone interview with him on Wed. This should be interesting...
hey
i just got in interview for an internsip (im a soph. in ECE).
the internship is in validation engineering < - are there any specfic questions for that ??
Also what are some analog questions they could ask ?
i also have to review my digital logic specifically sequntial logic, flip flops etc -- > forgot it all since I have not done it in about one year ...
i just got in interview for an internsip (im a soph. in ECE).
the internship is in validation engineering < - are there any specfic questions for that ??
Also what are some analog questions they could ask ?
i also have to review my digital logic specifically sequntial logic, flip flops etc -- > forgot it all since I have not done it in about one year ...
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