Anyone heard of TRAM memory cells?

[rimshaker]

Very novel idea, i read one of the IEEE transactions on it. It's as fast as SRAM, but with the same density as DRAM! In terms of transistor count, DRAM uses 1 nmos and 1 capacitor, SRAM uses total of 6 transistors... very large area requirement. TRAM (Thyristor-based RAM) uses a single nmos transistor and 1 thyristor that's vertically fabricated. I think the novel part is how they came up with the idea of using the leakage current from the transistor to make the thyristor remain in the active state!! Wow... and to think that leakage currents were always thought of as natural waste. I already sent off some resumes for this startup company in CA... wish me luck.

 

[Elledan]

Hmm... I'm just a newbie when it's about RAM, but this TRAM does sound suspiciously much like 1T-SRAM

 

[CTho9305]

<< Hmm... I'm just a newbie when it's about RAM, but this TRAM does sound suspiciously much like 1T-SRAM >>


agreed. the game cube uses it.

 

[crypticlogin]

<<

<< Hmm... I'm just a newbie when it's about RAM, but this TRAM does sound suspiciously much like 1T-SRAM >>


agreed. the game cube uses it. >>



Hmm... California startup "creates" and patents new memory design technique, only to later find that technique was already preexisting. So rimshaker, this startup isn't called RAMBUS by chance?

 

[StandardCell]

<< Very novel idea, i read one of the IEEE transactions on it. It's as fast as SRAM, but with the same density as DRAM! In terms of transistor count, DRAM uses 1 nmos and 1 capacitor, SRAM uses total of 6 transistors... very large area requirement. TRAM (Thyristor-based RAM) uses a single nmos transistor and 1 thyristor that's vertically fabricated. I think the novel part is how they came up with the idea of using the leakage current from the transistor to make the thyristor remain in the active state!! Wow... and to think that leakage currents were always thought of as natural waste. I already sent off some resumes for this startup company in CA... wish me luck. >>



Using leakage currents in that way is really innovative! I give them credit. How many additional process steps are used to make the RAM? Every additional process step reduces yield, so the question is, is it really economical? Also, are they using a BiCMOS-type process to do this? Finally, what area savings are realized versus a traditional 6-T SRAM cell in the same process, as well as performance hits/improvements?

BTW, this DEFINITELY is NOT the same thing as 1-T SRAM, just a different way to do a smaller SRAM without resorting to out-and-out trench caps like in DRAM or the standard 6-T.

 

[pm]

That's actually a really interesting idea. Based on the description of using a thryristor to store state, it's definitely not 1T-SRAM which is similar to DRAM and uses a capacitor to store state.

 

[rimshaker]

Rambus???! Cmon, give me a little credit here... TRAM is totally new at this stage. MRAM (magnetic ram) is even further off right now, but that's another story. TRAM is said to be economical since it uses the same process as normal CMOS, with a few minor upgrades. No BiCMOS here... no BJT's. I'm sure in terms of area/density, it's almost just like DRAM, only the capacitor is now a thyristor.... a vertical thyristor. So the space should be about the same. The only major modification i saw was the addition of an extra Word-line that's used only during write ops. So there's 1 bit-line, and 2 word-lines. Speed is improved further by using a cylindrical thyristor, and even more by reducing its thickness.

 

[StandardCell]

<< TRAM is said to be economical since it uses the same process as normal CMOS, with a few minor upgrades.
>>



Hmmm...that's interesting. I just wonder how many additional steps there are and WHAT they are...



<<
No BiCMOS here... no BJT's.
>>



I only asked because sometimes they fabricate some structures using BiCMOS that aren't normally available in standard CMOS, like building well inside well type things like they do for a regular BJT, and then tap them off.



<<
I'm sure in terms of area/density, it's almost just like DRAM, only the capacitor is now a thyristor.... a vertical thyristor. So the space should be about the same. The only major modification i saw was the addition of an extra Word-line that's used only during write ops. So there's 1 bit-line, and 2 word-lines.
>>



That's really good. This could be revolutionary.



<<
Speed is improved further by using a cylindrical thyristor, and even more by reducing its thickness. >>



Hmmm...cylindrical implies a round shape. Does the lithography at the sizes they are designing at support drawing truly round shapes (or for that matter angles more granular than 45 degrees)?

Actually, could you post the location or reference of the article/paper where you found this? I'd be really interested in reading it.

 

[CTho9305]

<< That's actually a really interesting idea. Based on the description of using a thryristor to store state, it's definitely not 1T-SRAM which is similar to DRAM and uses a capacitor to store state. >>



just noticed that. interesting idea anyone have links where we can read more?

edit:
1. a pdf.
2. the website

 

[rimshaker]

Have fun guys...

www.t-ram.com/about/iedm99.pdf

 

[pm]

Let's see, pending on the non-volatile memory horizon we have (and this is off the top of my head, so correct me where I am mistaken):

FRAM - ferroelectric (change the magnetism of the storage node with electromagnetism)
MRAM - magnetic (change the magnetic polarizatoin of the storage node with eletricity/heat)
OV-RAM - ovuonic (sp?) - change the resistance of the storage node by literally melting it and then letting it cool down at different speeds
tri-state Flash - going from storing two-bit per cell (ie. Intel's StrataFLASH), to three bits

This is the first replacement for DRAM/SRAM that I have heard of though.