Anybody have info on IVB transistor count for various dies?

[Hulk]

There seem to be 4 different IVB dies as can be seen here but the transistor count for only one is listed. I've been reading up getting ready for Haswell and was wondering if anyone ever came across the info for the count for the other cores?

http://en.wikipedia.org/wiki/Ivy_Bridge_(microarchitecture)


One other thing... The improved loop stream detection that was introduced in Nehalem... When a software loop is detected does this mean that for those instructions the pipeline that they must travel through can be shortened since some stages are bypassed?

 

[TuxDave]

One other thing... The improved loop stream detection that was introduced in Nehalem... When a software loop is detected does this mean that for those instructions the pipeline that they must travel through can be shortened since some stages are bypassed?

In my simplistic view of it...

Default way of doing things:
Step 1) Instruction cache stores all the instructions you want to go through
Step 2) Figure out what the next instruction is supposed to be
Step 3) Read the next instruction and decode it into CPU controls
Step 4) Ship it and do the instruction

For software loops, the first three steps do the same thing on the same series of instructions over and over again. What the loop stream detector does is basically store the past N decoded instructions and when a loop is detected, turn off #1-3 and just read it over and over from the pile of stored decoded instructions.

So what do you get? You get to save some power, that's good. You get some side effects for performance too. There are some cases in the "figure out what to do next" and "read the next instruction" that causes the CPU to hiccup. Now we get to skip that and just get a nice steady stream of post-decoded instructions.

To support bigger loops, you need a bigger N and so you do a tradeoff on performance and power.

At least that's how I see things.

 

[Yuriman]

I always assumed Intel only made 2 chips and disabled features depending on what it was to be sold as. An i5 should have the same number of transistors as an i7 or any 4 core Xeon.

I suspect the dual core mobile i7's roll off the i3 assembly line.

 

[Tsavo]

I suspect the dual core mobile i7's roll off the i3 assembly line.

That's probably a sound suspicion. Intel is making pretty good bank selling low-endian desktopish unfused dualies in the mobile space.

 

[Hulk]

While they do scavenge their higher end parts for the low end by disabling some L3, lower clocks, turn of HT, turn of Vx, Vd..., etc they also do produce smaller die varients of the same basic design as space on the wafer is quite expensive. As noted in Wiki there are four Ivy die variants and I believe I remember reading something about that on Anandtech but I can't seem to find it.

As Intel has moved from 2nd place (pre Conroe) they have become more and more secret about their products. With Conroe they basically gave away the store to Anand ahead of time because they needed to get the fact that they had a ground breaking AMD beating chip ready to blast out of the gates.

Through Penryn, Westmere, and Nehalem it seems as though Intel still viewed AMD as somewhat of a threat. That seemed to change a bit with Sandy and even more with Ivy as many details of these parts aren't being disclosed. There is no reason to. They don't have to actively sell the fact they they are on top anymore.

Beside pricing and slowing advances this is another side effect of a less competitive AMD. We get less info about the products. Which of course is a shame for us enthusiasts who like to know what's going on in there.

 

[SPBHM]

I always assumed Intel only made 2 chips and disabled features depending on what it was to be sold as. An i5 should have the same number of transistors as an i7 or any 4 core Xeon.

I suspect the dual core mobile i7's roll off the i3 assembly line.

4 dies for IB

and from that they can disable different parts,

I think all mobile I3s-i5s use the 4MB l3 die (with 1MB disabled), while mobile Pentiums and Celerons uses the 3MB l3 die (the same used for desktop i3s, apart from the 3225, but again with some l3 disabled),
also probably the 3570K uses the 8MB l3 die, while the 3470 use the 6MB one (because of the different IGP)?

 

[Hulk]

SPGHM,

Thanks. Do you have a link for that diagram?

 

[kimmel]

Through Penryn, Westmere, and Nehalem it seems as though Intel still viewed AMD as somewhat of a threat. That seemed to change a bit with Sandy and even more with Ivy as many details of these parts aren't being disclosed. There is no reason to. They don't have to actively sell the fact they they are on top anymore.

Beside pricing and slowing advances this is another side effect of a less competitive AMD. We get less info about the products. Which of course is a shame for us enthusiasts who like to know what's going on in there.

AMD is not viewed as a threat anymore but that has very little to do with the amount of information coming out of Intel. The mobile market is smoke and mirrors so Intel has decided it wants/needs to play that game as well. They won't publicly release data because anything they say can and will be used against them. This is much less to do with AMD than it is to do with the new competition.

If you really want Intel to jabber on and on about new upcoming things then you want less competition. Not more.

 

[Arachnotronic]

That's probably a sound suspicion. Intel is making pretty good bank selling low-endian desktopish unfused dualies in the mobile space.

No. The mobile chips need to be at much lower TDPs, so if anything the mobile chips are the cream of the crop.

 

[Hulk]

AMD is not viewed as a threat anymore but that has very little to do with the amount of information coming out of Intel. The mobile market is smoke and mirrors so Intel has decided it wants/needs to play that game as well. They won't publicly release data because anything they say can and will be used against them. This is much less to do with AMD than it is to do with the new competition.

If you really want Intel to jabber on and on about new upcoming things then you want less competition. Not more.

Understood. Let me clarify. Intel has no problem blabbering on about how good they are when they know they have crushed the competition. When they have a real game on their hands they zip up. You're right.