• We’re currently investigating an issue related to the forum theme and styling that is impacting page layout and visual formatting. The problem has been identified, and we are actively working on a resolution. There is no impact to user data or functionality, this is strictly a front-end display issue. We’ll post an update once the fix has been deployed. Thanks for your patience while we get this sorted.

Any Verilog experts out there????

DAM

Diamond Member
Well, we just got into Verilog and I am totally lost cause well we don't have a book or have had a very good class on this.



So anyone out there know verilog and is willing to help a brother out.





dam()
 
Have you looked at the Verilog Manual? you can find it by searching on google. Are you using the behavioral simulator or the logic simulator?
 
yeah i think i have, there arent many resources out there, do you have any which you recommend? or any books?





dam()
 
Back
Top