Any Silicon Gurus Here? :) How Complicated Would it Be To....

[AGodspeed]

...fab a .13-micron SOI processor with 754 or 940 pins, an integrated heat spreader, a die size of 104mm^2 or more among many other things. If you're not already aware, I'm referring to the ClawHammer and SledgeHammer processors. I'm just wondering approx. how difficult it would be to fab these babies (what problems would likely be encountered)? How long would you guess it to take for a process like this to fully mature?

Just curious.

For technical specs on "Hammer", go here

 

[Superdoopercooper]

I saw that article today on AT... pretty amazing. That is going to be one expensive piece of silicon.

 

[FlamingPanther]

I'm not sure, I think AMD is finally getting to where they need to be.

Anand said it only took them a month to Tap the samples out.

Thinking of how many transistors it has, thats some feat.

I think the only problem would be yields or clock speed,
and even then I don't think they will have to big a problem with the yield, as long as there is no wierd math error a 'la early pentium.

The clock is the only thing that concerns me, meaning AMD would not disclose the clock, anand and other sites guessed at .8-1 Ghz,
which is half to less than half of they target clock.

One thing that impresses me is that the Sledge has dual integrated 128 Bit DDR controllers.
But thats getting off topic.

Another problem I think is AMD trying to get software makers to compile products to run on x86-64,
Its gonna be harder than I think AMD realizes.

We'll have to wait and see.

FP

 

[rimshaker]

One thing for sure is that they weren't mass produced. Most likely they were carefully fabricated in a very highly controlled manner... a lot more 'manual interaction' rather than the usual automated process. The SOI process itself is difficult because such an ultra-thin uniform insulation layer is very hard to fabricate. The 0.13u shrink is a feat unto itself as well, but not as fragile as the SOI process, it's simply a scaling issue. Things get MUCH more difficult below the 0.10u process.

 

[AGodspeed]

<< One thing for sure is that they weren't mass produced. Most likely they were carefully fabricated in a very highly controlled manner... a lot more 'manual interaction' rather than the usual automated process. The SOI process itself is difficult because such an ultra-thin uniform insulation layer is very hard to fabricate. The 0.13u shrink is a feat unto itself as well, but not as fragile as the SOI process, it's simply a scaling issue. Things get MUCH more difficult below the 0.10u process. >>

If that's the case, then what exactly are the benefits of SOI? Why would AMD and IBM (among others) choose SOI. Is there really a great performance as well as thermal advantage to SOI?

Thanks for the reply.

 

[rimshaker]

<< If that's the case, then what exactly are the benefits of SOI? Why would AMD and IBM (among others) choose SOI. Is there really a great performance as well as thermal advantage to SOI? >>



SOI is not a revolutionary technology, it's been around for a long time actually. Think of SOI more of as a patch to help increase cpu performance. Basically how it works is that instead of transistors and devices being fabricated directly on silicon, they are built on top of a very thin layer of oxide. And this oxide is layered on top of the silicon instead. This thin oxide layer must be totally uniform. In terms of circuit performance, this structure reduces parasitic capacitance, lowers leakage current, and hence.... increases switching speeds and performance. And at the same time, operating temperature is reduced too.

 

[EmMayEx]

Since I work for a company that makes semiconductor manufacturing equipment I'll take a shot.

Die size is to a large degree irrelevant as far as "difficulty to manufacture" goes but it affects economics since you get fewer devices per wafer and killer defects have a larger hit on yeild. One killer defect per wafer only reduces yeild by 1% if there are 100 devices per wafer but that is doubled if there are only 50 devices per wafer. Packaging larger die sizes becomes more difficult and expensive but while 104 mm^2 is large it isn't outside the capabilities of "standard" packaging equipment.

The biggest questions would be the 0.13 micron process and the SOI process. Thin oxide layers are not that difficult to create and control. Gate oxides are approaching 10 nm thicknesses for CMOS process which is challenging from a manufacturing standpoint but not exactly bleeding edge. The 0.13 micron procss has been mastered by some manufacturers (Intel for example) but it is the leading edge as far as mass production goes. I'm not aware of anyone mass producing at the 0.10 micron node yet but I know there are test lines and plans to operate here by mid 2002.

Since this requires no "new" technology to implement it is just a matter of getting the equipment installed and set up. This is far from trivial and the turnaround depends a lot of how well the fab managers do their job and how well purchasing did their job in picking appropriate equipment. If they've produced samples then scale up should be a matter of months. Contrary to what someone mentioned earlier, yeild will increase dramatically with mass production techniques. The use of SMIF pods and automated transport of wafers between processing stations will greatly reduce human intervention which is the largest source of contamination and defects in a fab.

Still there is a lot of tweaking that must go on and there will be statistical process control models to develop before yeild can be optimized. I'd guess it will be a year or more before the process is "mature" but there will be constant adjustments to the basic process early on so the "mature" process may differ significantly from the prototype process used to make the first few samples. Still, the technology has been used in mass production elsewhere so the potential for hidden pitfalls is fairly low as long as the people running the fab are competent. Time will tell.

Max L.

 

[Eskimo]

<< Since I work for a company that makes semiconductor manufacturing equipment I'll take a shot.
>>



Hope it's not Perkin-Elmer after that hit their stock took yesterday



<< Gate oxides are approaching 10 nm thicknesses for CMOS process which is challenging from a manufacturing standpoint but not exactly bleeding edge. >>



I think you either made a typo or are mistaken. 10nm=100A. Current Gate oxides are well sub 20A in advanced CMOS. .13 will probally require around 15A GOX.




<< The 0.13 micron procss has been mastered by some manufacturers (Intel for example) but it is the leading edge as far as mass production goes. I'm not aware of anyone mass producing at the 0.10 micron node yet but I know there are test lines and plans to operate here by mid 2002.
Since this requires no "new" technology to implement it is just a matter of getting the equipment installed and set up. >>



Are you still speaking here in regards to .13 or are you talking about .10 now? Because my understanding is that the consensus of the industry is to move to 193nm for .10 which has introduced a slew of problems with ARCs and immature resist technologies. I haven't seen a good 193nm resist that has a good etch selectivity yet. But like you said we aren't there yet so they have a little time to figure that out.



<< I'd guess it will be a year or more before the process is "mature" but there will be constant adjustments to the basic process early on so the "mature" process may differ significantly from the prototype process used to make the first few samples. >>



Speaking from experience, unfortunately in the microprocessor world few products get to achieve 'mature' levels. By the time you have your process tweaked and your yields coming up it's time to ramp the product to the next speed grade and/or introduce an entirely new product. It's frustrating but fun

 

[idgaf13]

To get a better perspective on this topic and the interaction with other components go back to when Intel was promoting the P4 and Rambus.
Intel claimed low micron sizes were not the issue that technology such as Rambus would be the next great thing,we have seen the results of that.
Rambus is dying ,long live DRAM as single or double or quad.
Intel also implied that a copper process was not necessary WRONG ,copper is an absolute as line sizes decrease.
As is a better dielectric constant ,which so far can only be acheived by increasing the concentration of oxygen in the silicon.
IBM was the first with a copper process for cpu's.
when Motorola ran into trouble making G4 chips for Apple they asked for help from IBM.
IBM redesigned the architecture of the chip and speeds doubled.
As IBM has been at the forefront of the copper process from the start with motorola running a poor second and Intel playing catch up.
The question becomes who can afford to produce future generations of chips ?
Intel is heavily invested in "small" wafer fabs that rely on aluminum not copper.
The P4 is to large and consumes to much power no matter how you look at it.
AMDs Dresden plant was designed with copper in mind and they are working on robotics for chip production.
Yes ,the Hammer series will be good out of the gate reggaredless of MHz rating.
But how do you measure performance of a chipo that does 32 and 64 bit vs a chip that does only one or the other ? A marketing nightmare for sure.

 

[IaPuP]

As IBM has been at the forefront of the copper process from the start with motorola running a poor second and Intel playing catch up.

A quck comment about this.

First, Intel's .18 Aluminum process was considered much more highly developed than IBM's .18u copper process.

I've heard that Intel's .18u Al process was arguably faster than IBM/Mot/AMD's .18u Copper process and even TSMC's 0.15u process.

Even as recent as a few months ago, those beliefs have been expressed by people who know more than I about the relative merits of each company's manufacturing.

Eric

 

[Shalmanese]

Well, the AMD hammer is not designed for the average Joe so (hopefully) the marketing will be to more savvy people.

If not, they are going for the chunk of the crowd buying SUN processors anyway so 1 Ghz is still pretty respectable.

 

[Sohcan]

<< Intel claimed low micron sizes were not the issue >>

Um, right...show me where Intel wanted to break the four-decade long trend of decreasing gate size. So much for the continued 30% linear reduction in gate size for 10 nanometer lithography in the next decade?


<< Rambus is dying ,long live DRAM as single or double or quad. >>

RDRAM and DDR SDRAM are both types of DRAM.


<< Intel also implied that a copper process was not necessary WRONG >>

They never said that, their position was that the benefits of copper did not outweigh the costs on their .18u process; I've heard the same argument from more than a few EEs. As its a moot point now, it's only a point of contention for people with an axe to grind.


<< Intel is heavily invested in "small" wafer fabs >>

??? Intel is already shipping MPUs from their 300mm fab in Oregon, only the second 300mm facility in the world. Their site in New Mexico is already being converted.


<< that rely on aluminum not copper. >>

Their .13u facilities (there are 5, IIRC) use copper.


<< The P4 is to large >>

Wonderful, another enthusiast obsessed with die size. Did you ever consider functional yield, speed yield, packaging, assembly, testing, fallout, materials technology, wafer size, R&D, marketing costs, ASP, and target market as factors in cost?


<< and consumes to much power no matter how you look at it. >>

That's spurious reasoning. And other high-end MPUs don't consume a lot of power? The 1.67 GHz XP dissapates 70W, compared to the 2GHz Willamette's 75W and the 2.2GHz Northwood's 55W.

If you'd like to participate in the HT forum, please take the Intel vs. AMD crap elsewhere.

 

[EmMayEx]

Eskimo,

I don't work for Perkin Elmer, my company (Akrion) is privately held. However, I wouldn't want to wager much on the survivability of any small semiconductor equipment manufacturer in this market. Fortunately, things seem to be improving albeit slowly.

You are correct, gate oxide levels for advanced CMOS processes are approaching 1.0 nm (10A) not 10 nm. At some point you start to run into the problems inherent in creating monolayers of oxide or oxynitride since you are getting close to atomic sizes. I think there is still some room to reduce oxide layer thickness below 10 A, but not much (6 A sticks in mind as the diameter of a silicon atom, but I'm not sure what the lattice dimensions are in SiO2).

Lithography is certainly a major roadblock to commercializing the 0.10 micron node. It sounds like there are some bugs to be worked out of the resists yet in order to talke full advantage of the 193nm litho equipment and phase shift masks. However I think the 0.13 micron node is "proven" technology since a number of manufacturers are running commercial lines at 0.13 micron. There is no new technology to develop in order to commercialize 0.13 micron semiconductor fabrication however I have not seen "commercial" implementation of 0.10 micron processing. I'd be interested in how the first manufacturer manges to pull this off while maintaining competitive yeild rates. It's important to differentiate what has been done a few times in the lab from what can be done thousands of times a day, 365 days a year in a controlled enough fashion to make a few bucks off it.

It looks like AMD is well on the way with the hammer line of processors but my wild ass guess is that it will be a year before they are comfortably producing parts in a high yeild process that meet their design clock frequency and other specs. By then, as you pointed out, the next generation of processors will most likely have started production in sample quantities. Such is the nature of this business.

Max L.

 

[idgaf13]

The most difficult part of the copper process is the polishing after deposition of the metal.
If a "hole" exsists an electron will traverse into that hole and increase its depth ,
subsequent similar events will cause a hole into the next layer of material.
Research at IBMs process looking for the Dual-Damascene polishing process

As far as dealing with atomic sizes IBM has successfully developed a technique for depositing molecules of oxygen on silicon at a depth of two atoms.

I am not an IBM zealot ,their marketing stinks and subsequently their R+D people never get the pat on the back they deserve.
I recall they licensed a SCSI technology to Quantum and quantum had a product out the door three months ahead of IBM.
That is a problem.

 

[Acanthus]

As i am not sure of the process the benchmark was done, i wont say this with any certainty. IBM claims their new Power4 chip running on their new server is supposed to be 4x as fast as 64 Intel Xeon Processors at 1.7GHZ. There are about 200 ways you could fake this in a benchamark, and they didnt name the benchmark it was done in, but if you even halve their claim, they are way ahead of motorola and intel...