Originally posted by: VirtualLarry
Are you suggesting that Intel has left out all of the tweaked prefetch logic that is present in Penryn, in Nehalem? That would seem strange to me.Originally posted by: Idontcare
Originally posted by: nerp
Watch ASRock come out with a board with DDR2 and 3 memory slots.![]()
I pity the fool who spends the $$ on a Nehalem to turn around and cripple the system by choking it with a bunged-up dual-channel DDR2 mobo.
Penryn is pretty much indifferent to the DDR2/DDR3 business end of the mobo thanks to the prefetchers and massive L2$...Nehalem will no doubt be a tad more sensitive to the memory sub-system if you actually intend to utilize the CPU.
Not by any stretch of the imagination am I suggesting that.
But the engineers certainly designed the chip to require a certain bare minimum bandwidth to go along with the low latency of the IMC...drop below that minimum and you will no doubt bottleneck the CPU's abilities provided you are doing something with those 8 threads beyond checking email and uploading photos to snapfish.
What I am suggesting is that this bare minimum bandwidth ought to lie somewhere above dual-channel DDR2-1066 and below dual-channel DDR3-1333.
If the minimum lies any lower than that it would imply Intel wasted valuable xtor's (needlessly bloating the Nehalem die) in beefing up prefetchers and L3$ by designing for a bare-minimum bandwidth that likely will easily be surpassed by mainstream systems.
If DDR2 is good enough to support 8 threads at peak utilization then it would also imply that triple-channel DDR3 provides negligable benefit to bloomfield out of the gate, which I highly doubt will be the case.
And if triple-channel DDR3 provides noteworthy benefit then not having triple-channel DDR3 ought to provide a noteworthy performance degradation.
Are my suggestions any clearer now?