any circuit folks? simple nmos/pmos+cap question - cap discharge/charges when xtor are off?

[LordSnailz]

Any ee folks in the house, being thinking about this for the past hr and I couldn't figure it out.

hoping the "PICS" would draw more people in -
http://pics.bbzzdd.com/users/lordsnailz/cap_circuit.jpg

What I don't understand is why the capacitor discharges when the PMOS transistor is turn off? There shouldn't be a path to ground, both the PMOS and NMOS are off. Leakge?

Second question is why does the the capacitor charges back up ater it's been full dischage, ie 4ms in the graph. THe NMOS and PMOS is off, but the capacitor charges back up to 1.4V? How and by who?

Is there something that I'm missing as to why the cap. is going back to some steady state value?

Any suggestions or inputs? Thanks in adv.

 

[dighn]

I would guess it's leakage. looks like whenever both transistors are off, the capacitor tends toward a value right between 0 and +v which is what you would expect if the turned off transistors are modeled as having high resistances.

 

[LordSnailz]

hmm, then how is it getting charged back up to that 'magically' value when both transistors is off and it's already discharged. At around 4ms, it's starting charging up, I'm not sure how or by what ...

 

[imported_mateo]

I would start by checking the flux capacitor...then maybe the supression ramicator.

 

[LordSnailz]

flux cap, suppression ramicator ... hm not familar with this terms and I'm not sure if they're properties I can adjust in swcaiii

 

[dighn]

Originally posted by: LordSnailz
hmm, then how is it getting charged back up to that 'magically' value when both transistors is off and it's already discharged. At around 4ms, it's starting charging up, I'm not sure how or by what ...

well if both transistors when off are modeled as having high resistances of equal value, then they form a 1/2 voltage divider and would charge the cap to that.