Another VHDL question

[Deeko]

ok, here's my code...it generates an 8x8 grid of adders and passes values through them. However...nothing seems to be mapping to the adders. why??

 

[Deeko]

I've isolated the problem. Its these lines here, they aren't working. I don't know why....its syntactically correct...

west(row_index) <= east(row_index);
north(col_index) <= east(row_index);

 

[itachi]

the syntax is correct, but you get unexpected behavior..
west(row_index) <= east(row_index);
north(col_index) <= east(row_index);
when col_index is going through it's first iteration, all the columns get assigned the value in the row.. when col_index gets incremented, all the columns get assigned the value in the next row.. and what you have is a signal with multiple drivers, which leads to a call on the resolution function (when you get X in place of 1, it's cause you're using std_logic_1164 improperly).