Anandtech article about ARM floating point perf

[rahulgarg]

Hi folks. As you may know, I am a relatively new author here. I recently wrote an article about floating point perf on ARM processors:

http://www.anandtech.com/show/6971/exploring-the-floating-point-performance-of-modern-arm-processors

Let me know if you have any feedback.

 

[BrightCandle]

I thought it was an excellent piece. I would love to get hold of the code you used for determining the FP throughput per clock.

 

[poofyhairguy]

I thought it was really good as well. Only thing I wish it added was a bit of historical perspective with x86- IE: how does current ARM stack up against early X2 or Core Duos instead of i5s?

We all know that mobile tech is slower than modern desktop/laptop tech, but I assume that my S4 is more powerful than my first Macbook and that fact is amazing.

 

[ChronoReverse]

It's always good to see your work, codedivine!

 

[rahulgarg]

Thanks for the kind words everyone. About the code, I do plan to open-source it at some point within a few months, after perhaps we get 1 or 2 more articles out.
It is not exactly rocket science though. With the description in the article, and a little bit of experimenting, you can figure it out pretty easily. It is a standard technique, so you should be able to find articles and maybe existing code about it on the webs.

Comparisons with x86: Well, I wanted to avoid detailed comparisons in this article.
Generally cross-ISA comparisons about instruction throughputs are a minefield. Ideally cross-ISA comparisons are best done at the application level rather than synthetic instruction throughput level.

Anyway, since you asked, here is some data from memory:

Core 2 Duo: 4 DP flops/cycle, 8 SP flops/cycle
Nehalem: 4 DP flops/cycle, 8 SP flops/cycle
k10: 4 DP flops/cycle, 8 SP flops/cycle
Sandy/Ivy: 8 DP flops/cycle, 16 SP flops/cycle

 

[poofyhairguy]

Comparisons with x86: Well, I wanted to avoid detailed comparisons in this article.
Generally cross-ISA comparisons about instruction throughputs are a minefield. Ideally cross-ISA comparisons are best done at the application level rather than synthetic instruction throughput level.

Ah ok good to know, thanks

Anyway, since you asked, here is some data from memory:

Core 2 Duo: 2 DP flops/cycle, 4 SP flops/cycle
Nehalem: 4 DP flops/cycle, 8 SP flops/cycle
k10: 4 DP flops/cycle, 8 SP flops/cycle
Sandy/Ivy: 8 DP flops/cycle, 16 SP flops/cycle

Oh wow that is awesome. Thank you again for the article and further information!

 

[rahulgarg]

My C2D data was wrong, edited the post above.

 

[poofyhairguy]

My C2D data was wrong, edited the post above.

Oh wow, so we aren't even close to having Core2-level power in our pocket then?

 

[ChronoReverse]

Oh wow, so we aren't even close to having Core2-level power in our pocket then?

Well, it wasn't exactly surprising

 

[poofyhairguy]

Well, it wasn't exactly surprising

My dumb ass actually believes the Nvidia slides.

Where are we then? Katmai level? Northwood level?

 

[ElFenix]

My dumb ass actually believes the Nvidia slides.

Where are we then? Katmai level? Northwood level?

P54c on a per clock basis.




Note: i have no idea what i'm talking about but plan on reading the article when i'm off the phone

 

[poofyhairguy]

P54c on a per clock basis.




Note: i have no idea what i'm talking about but plan on reading the article when i'm off the phone

Oh wow, only a Pentium 1 level? So I am rocking a 2Ghz quad core Pentium 1?

 

[ChronoReverse]

I'd say Pentium III level actually. Probably higher in absolute terms. (assuming we're talking about the A15).

 

[poofyhairguy]

I'd say Pentium III level actually

Per mhz or overall?