- Dec 25, 2013
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EETimes: Silicon Lacks Clear Metrics
A lot of confusion, though.
Earlier HVM and superior metrics across the board: I'd say still a good 2 year lead, heuristically.
A lot of confusion, though.

Earlier HVM and superior metrics across the board: I'd say still a good 2 year lead, heuristically.
TSMC has been clear its 16nm process uses its 20nm back-end technology with FinFET transistors layered on top. At its recent symposium in San Jose it said its 7nm node will be 1.63 times denser than its 10nm process, which is well short of 2x that would result from 0.7x linear scaling in both dimensions, yet the node name was scaled 0.7x, said Wei of Chipworks.