AMD's palomino and mustang.

[Pyro]

I read this article over at ViaHardware that discusses AMD's next gen CPUs (http://www.viahardware.com/palomino.htm -- very interesting) but it didn't mention the chip's L2 bus. We all know that even the Tbirds use a 64bit bus while the CuMines use a 256bit. Does anybody know how wide the bus is gonna be on the palomino and mustang?

 

[Mark R]

I don't know, but my guess is that as long as AMD keep their 128 kB L1 cache, they will retain a 64 bit L2 bus.

Simply put, the L1 has a sufficiently high hit rate, that for most of the time the L2 cache bandwidth is more than sufficient. Why expand the bus, when it isn't a significant bottleneck?

 

[cdrakejr]

I haven't seen any solid info released yet, but here is a very technical article, PDF format, that discuss some possibilities and the resulting performance:

http://www.chip-architect.com/mw.pdf

This is a lengthy article comparing Mustang and Willamette based on available info at the time. Page 4 has some discussion on your question.

 

[cdrakejr]

Sorry, left a letter out of the URL in my first post, should be:

http://www.chip-architect.com/mw.pdf

First entry now corrected!