AMD's HyperTransport vs old FSB's how do they work now

[icon501]

Ok got a question don?t know if anyone has thought to ask this yet.
But on older types of motherboards the cpu's MHz was computed by the MHz of the fsb * the cpu's clock multiplier.
But scence the new AMD's Opteron uses a totally different type of buss. How is there MHz generated? Or worse yet how can someone over clock the cpu??

Any insight into this would be most helpful

Thank you for your time and info...


Hk

 

[ViRGE]

Humm, that's a really good question. My gut instinct is that the CPU is a multiple of the memory controller frequency, which isn't an HT connection BTW, but that doesn't mean it is that way, and I don't have the documentation in front of me. If you don't get any responses, try the Highly Technical forum, there might be someone there that knows the answer.

 

[Lord Evermore]

I don't know how the CPU's speed is configured for Hammer, but it's technically not required that it have anything to do with a "frontside bus". The frontside bus clock is just based on a clock built into the chipset (used to be a physically separate crystal on the motherboard way way way back, you overclocked by changing the crystal). In fact all the busses are based on that really, otherwise you couldn't have a PCI and AGP bus lock, if they were dependent on the frontside bus speed. So as long as they still have a clock generator somewhere, all the bus speeds can be calculated based on speed relative to the base clock frequency. Changing the processor speed would still involve changing the multiplier, or increasing the speed of the "frontside bus" if they continue to use that as a reference point. Since the clock crystal will always be at the same speed, there will probably be a setting which takes the place of the frontside bus speed, so the CPU would be a multiplier of this new "reference speed", and you could increase that. Other things like the PCI and AGP bus would be based only on the base clock if you locked them.

There isn't really a "frontside bus" in the Hammer line now, not in the sense we're used to. The HyperTransport bus is just a data bus, it's versatile and can be used for all sorts of things. They could make the HT bus to the chipset run at any speed, independent of the speed of the CPU. In previous platforms, the bus speed was actually the speed of the connection between the northbridge and the CPU. Now they're just connected by a data bus (HT), just like having something stuck on the PCI bus communicates with the chipset.

There will supposedly be an option for chipsets to disable the built-in memory controller, allowing for upgrades without replacing the entire CPU. In those cases, the system will take on a more traditional design, but still uses HyperTransport for the CPU-chipset bus, so presumably could still have the high bandwidth link unrelated to the actual clock speed. The 16-bit HT busses allow 6.4GBps total throughput each, one of which will always be used for connecting to the northbridge presumably. Since chipsets like the nForce3 won't have two chips, there's going to be a huge reduction in the latencies and bandwidth concerns in an Opteron system. No more worries about whether the north to southbridge bus is fast enough, and presumably most of the integrated features won't use the PCI bus so they essentially get a direct path to the CPU.

[edit] Looking at the information on amd's site about the Opteron, they do say "up to" 6.4GBps per HT link, so it may be that they actually use the HT bus's clock speed to base the CPU speed on. So it would sort of take the place of the frontside bus speed setting. No real reason to do that of course, but it does mean that overclocking will still be the same, since they'll lock the multiplier you can only overclock by increasing both the HT bus speed and the CPU speed, rather than just the HT bus speed (which would be similar to using a lower multiplier with a faster frontside bus). Not that I expect there'd be much performance gain from more bus speed in this sort of system.

 

[AtomicAlien]

Originally posted by: Lord Evermore

There isn't really a "frontside bus" in the Hammer line now, not in the sense we're used to. The HyperTransport bus is just a data bus, it's versatile and can be used for all sorts of things. They could make the HT bus to the chipset run at any speed, independent of the speed of the CPU. In previous platforms, the bus speed was actually the speed of the connection between the northbridge and the CPU. Now they're just connected by a data bus (HT), just like having something stuck on the PCI bus communicates with the chipset.

There will supposedly be an option for chipsets to disable the built-in memory controller, allowing for upgrades without replacing the entire CPU. In those cases, the system will take on a more traditional design, but still uses HyperTransport for the CPU-chipset bus, so presumably could still have the high bandwidth link unrelated to the actual clock speed. The 16-bit HT busses allow 6.4GBps total throughput each, one of which will always be used for connecting to the northbridge presumably. Since chipsets like the nForce3 won't have two chips, there's going to be a huge reduction in the latencies and bandwidth concerns in an Opteron system. No more worries about whether the north to southbridge bus is fast enough, and presumably most of the integrated features won't use the PCI bus so they essentially get a direct path to the CPU.

[edit] Looking at the information on amd's site about the Opteron, they do say "up to" 6.4GBps per HT link, so it may be that they actually use the HT bus's clock speed to base the CPU speed on. So it would sort of take the place of the frontside bus speed setting. No real reason to do that of course, but it does mean that overclocking will still be the same, since they'll lock the multiplier you can only overclock by increasing both the HT bus speed and the CPU speed, rather than just the HT bus speed (which would be similar to using a lower multiplier with a faster frontside bus). Not that I expect there'd be much performance gain from more bus speed in this sort of system.

Almost right based on what I heard, there are supposed to be two 3.2GB/s channels to-and-from the processor giving about 6.4GB/s, yes. But in addition to that it has it's own dedicated 2GB/s channel to the AGP card.

 

[DeRusto]

Originally posted by: AtomicAlien

Originally posted by: Lord Evermore

There isn't really a "frontside bus" in the Hammer line now, not in the sense we're used to. The HyperTransport bus is just a data bus, it's versatile and can be used for all sorts of things. They could make the HT bus to the chipset run at any speed, independent of the speed of the CPU. In previous platforms, the bus speed was actually the speed of the connection between the northbridge and the CPU. Now they're just connected by a data bus (HT), just like having something stuck on the PCI bus communicates with the chipset.

There will supposedly be an option for chipsets to disable the built-in memory controller, allowing for upgrades without replacing the entire CPU. In those cases, the system will take on a more traditional design, but still uses HyperTransport for the CPU-chipset bus, so presumably could still have the high bandwidth link unrelated to the actual clock speed. The 16-bit HT busses allow 6.4GBps total throughput each, one of which will always be used for connecting to the northbridge presumably. Since chipsets like the nForce3 won't have two chips, there's going to be a huge reduction in the latencies and bandwidth concerns in an Opteron system. No more worries about whether the north to southbridge bus is fast enough, and presumably most of the integrated features won't use the PCI bus so they essentially get a direct path to the CPU.

[edit] Looking at the information on amd's site about the Opteron, they do say "up to" 6.4GBps per HT link, so it may be that they actually use the HT bus's clock speed to base the CPU speed on. So it would sort of take the place of the frontside bus speed setting. No real reason to do that of course, but it does mean that overclocking will still be the same, since they'll lock the multiplier you can only overclock by increasing both the HT bus speed and the CPU speed, rather than just the HT bus speed (which would be similar to using a lower multiplier with a faster frontside bus). Not that I expect there'd be much performance gain from more bus speed in this sort of system.

Almost right based on what I heard, there are supposed to be two 3.2GB/s channels to-and-from the processor giving about 6.4GB/s, yes. But in addition to that it has it's own dedicated 2GB/s channel to the AGP card.

I don't know too much about the HT implementations so all I can say is, "Nice"

 

[Lord Evermore]

I've seen nothing about any dedicated channel to the AGP card. The CPU's access to the AGP bus is through the "AGP Tunnel" or "northbridge" or "system chipset". For the AMD design, that'd be the AMD 8151 AGP Tunnel. The nForce3 integrates the southbridge functions and the AGP bus controller, which I think the VIA Hammer chipset does too. The CPU doesn't have a direct connection to the AGP bus, it connects to an AGP controller through one of the Hypertransport links. Opteron uses 2 HT links for interconnecting in multiprocessor, and the third link is used for connection to whatever I/O chipset is used. In actual usage, that means each CPU can only connect to one chipset, and other chipsets have to pass through the first one. So if a single processor board has an AMD 8151 AGP Tunnel, there has to be a "southbridge" which passes through the AGP Tunnel to reach the CPU. If there are two processors, then one could have the AGP Tunnel, and the other could have the "southbridge", which keeps the AGP Tunnel from being a possible bottleneck, but also means that traffic has to pass through one of the CPU's HT controllers to reach the other CPUs.

The AT article shows the layout here: http://www.anandtech.com/cpu/showdoc.html?i=1815&p=7