AMD X2 cache die size

[IntelUser2000]

If you search for AMD dual core die pic in google, you'll see a pic of X2 die. Here: http://www.a1-electronics.net/AMD_Section/CPUs/2005/AMD_Athlon64x2_Apr.shtml

Die size of X2 with 2x1MB L2 is 199mm2, and 2x512KB L2 is 147mm2. Which means at 90nm, 1MB L2 die size is 52mm2. Nothing much to think of there, until you look at this:
http://techreport.com/reviews/2005q2/pentium-xe-840/index.x?pg=1

The die size is 206mm2. That implies that the 1MB L2 cache is much smaller than the X2's. I found that its actually ~23mm2 for 1MB L2 in Prescott. Northwood is around ~30mm2 for 512KB L2 cache. 512KB cache for Northwood should be 15-16mm2 and 15x2=30, Prescott's cache has been made to sacrifice performance for die size reduction. However, we know Northwood's cache is very good in terms of latency. It implies Intel knows how to make extremely small caches with excellent performance.

What I can't believe is they wasted the die space by cramming all those transistors for logic that really give no performance increase. The little difference that would have made Prescott better than Northwood per clock hadn't happened since L1 and L2 latency is so high.

 

[coldpower27]

Hmm, I think it's known that Intel is superior with caches vs AMD, look at Dothan, it's 2MB of LV2 cache, and the whole die size of Dothan is 83.6 mm2, given an assumption that Dothan is about 60% cache, that is only about 50mm2 of space for 2MB of Cache.

On the single core Athlon 64's the difference in cache is about 30mm2 for Venice vs San Diego for 512KB of it.

I wouldn't call Prescott-2M 135mm2 vs Prescott 112mm2 completely fair in differences in cache, as Prescott-2M cache is slower then Prescott's. However judging by Dothan though, they can put in very dense AND very fast cache if they do so desire, the main issue is probably yield and costs.

From Manchester to Toledo though it seems that AMD cache density has improved at least a little.

I think I have an idea why Intel uses cache to increase performance, as simply they are very effective with them, and NetBurst Architecture was dependent on cache at least until the Prescott core arrived. Not to mention putting in cache helps leave a larger margin of errors, as you can deactivate cache and still sell a processor, but can't do squat if the defect is on the processor core itself.