Can anyone do a compare contrast between AMD's and Intel's SMP protocols? My vague understanding is as follows:
Intel: Basically puts two cache coherent processors on the same bus. Bandwidth to memory is shared between the two processors. Limitations are exactly because of this sharing mechanism, not enough bandwidth to satisfy two processors worth of data requests.
AMD: More advanced point to point protocol. Each processor gets full bus bandwidth per processor. How the hell this works, I have no idea. I can only imagine a huge switch in the memory controller that can service each processor independently. To me, this is making less sense, since a snoopy bus protocol of maintaining cache coherency would be completely eliminated, since the bus does not connect every processor and the snooping mechanism cant figure which lines to invalidate. This is unless there is a seperate invalidation bus, which means more wires, more complicated processors and is plain stupid. But full memory bandwidth to each processor would be huge.
In addition can anyone point me to a comparison/in depth review of Intel's AGTL+ vs. AMD/DEC's EV6 bus architectures. Im really interesting in finding out more about these SMP mechanisms.
Facebook
Twitter