AMD to launch Phenom II x4 975

[frostedflakes]

You do realize the difference between poor out-of-order execution, and no out-of-order execution, right? Your post implied the latter, which is completely false.

 

[VirtualLarry]

You do realize the difference between poor out-of-order execution, and no out-of-order execution, right? Your post implied the latter, which is completely false.

Nope, you're wrong. You were talking about OOO execution, he was talking about OOO load/stores. Different things.

 

[soccerballtux]

Nope, you're wrong. You were talking about OOO execution, he was talking about OOO load/stores. Different things.

Wonder what Intel did. You can't exactly have an out of order store if the operand hasn't been operated on yet.

 

[frostedflakes]

Nope, you're wrong. You were talking about OOO execution, he was talking about OOO load/stores. Different things.

If that's the case, surely you can understand my confusion. P6 was Intel's first general out-of-order architecture, and that's when he claimed this feature was introduced. The newer implementation he was talking about for out-of-order load/store operations wasn't introduced until the Core architecture, however.

I feel like we're arguing semantics here, but my understanding is that there's no middle-ground, a processor is either out-of-order or in-order. It doesn't support only one for some instructions, either all instructions can be reordered or they can't. The P6 was fully out-of-order, the Core is fully out-of-order, the K5 was fully out-of-order, etc. The Core, however, did introduce some changes that made out-of-order execution of some instructions more efficient. That doesn't mean it was impossible to reorder some load/store instructions before Core, though.