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Question Amd ThreadRipper 12nm I/O Die

nicalandia

Senior member
Jan 10, 2019
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Has anyone been able to delid a TR3000 CPU? Would be interesting to see if there is any difference between the 14nm I/O die found on Epyc and TR, not that the human eye can distinguish between 14 and 12 nanometers. Any efficiency benefits?
 

Markfw

CPU Moderator, VC&G Moderator, Elite Member
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May 16, 2002
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While I have 7 threadrippers, and 5 EPYC chips, there is no way I am going to even attempt to delid any one of them.
 

nicalandia

Senior member
Jan 10, 2019
246
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76
While I have 7 threadrippers, and 5 EPYC chips, there is no way I am going to even attempt to delid any one of them.
True, is there any of those TR and EPYCs based on Zen 2? Any chance of trying to perform a usage test based on same clocks? EPYCs having so much lanes will have them consume more power than TR
 

Hitman928

Platinum Member
Apr 15, 2012
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Has anyone been able to delid a TR3000 CPU? Would be interesting to see if there is any difference between the 14nm I/O die found on Epyc and TR, not that the human eye can distinguish between 14 and 12 nanometers. Any efficiency benefits?
 

Markfw

CPU Moderator, VC&G Moderator, Elite Member
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May 16, 2002
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I think he really can't do this effectively. The socket, using the torque guage, puts a LOT of pressure between the chip and the socket pins. Then the heatkiller (I have one) , normally puts a fair amount of pressure to get the sink to transfer from the HSF, which is soldered. So without the chip cover, we loose pressure and thermal transfer. Nothing is as it should be.
 
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Topweasel

Diamond Member
Oct 19, 2000
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Really it doesn't make sense for TR to have a different IO chip. Part of what made TR work is the fact that it was a low cost solution to enter the HDET market for AMD. Its using the exact same configuration as EPYC and while it is using less PCIe and memory controllers there is no way that AMD is making enough of these to offset the design costs for a more limited IO chip. TR also gives AMD a place to put defective IO dies where memory channels or PCIe controllers are bad.
 

nicalandia

Senior member
Jan 10, 2019
246
147
76
Really it doesn't make sense for TR to have a different IO chip. Part of what made TR work is the fact that it was a low cost solution to enter the HDET market for AMD. Its using the exact same configuration as EPYC and while it is using less PCIe and memory controllers there is no way that AMD is making enough of these to offset the design costs for a more limited IO chip. TR also gives AMD a place to put defective IO dies where memory channels or PCIe controllers are bad.
I would say that for the same reason that Ryzen 3000 I/O chip is built on 12nm, Higher memory clock(cant recall from where I read that) thus higher performance

TR3000.jpg
 
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