- Aug 9, 2002
- 16,665
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http://www.dailytech.com/Article.aspx?newsid=6918&red=y#comments
[*]the IMC can access memory in 64-bit channels (72-bit if you use ECC)[/li]
This way it is possible to read and write data simultaneously, or improve efficiency for irregular access patterns which increasingly occur in a quad-core environment
[*]Due to split power planes, the IMC can be clocked down independently of the CPU cores, along with reduced voltage[/li]
This also enables CPU overclocking without touching the memory frequency, something that may appeal to enthusiasts. These features are again dependent on Socket AM2+ and F+ platforms.
[*]quad-core design benefits from the internal crossbar switch the backbone of communication inside the K10 CPU. [/li]
With Intel's current quad-core design there are cases where data needs to travel over the FSB -- in AMDs case all inter-CPU communication takes place on-die.
[*]Amato also mentioned an array of power saving measures which, in sum, allow AMD to deliver a quad-core CPU in the same thermal envelope as today?s dual-core CPUs[/li]
[*]K10 adds the capability of independently clocking all the CPU cores.[/li]
This feature could possibly be abused by overclockers to overclock a single core above the specified levels. Amato clarified that AMD doesn't endorse overclocking, but acknowledges there are people interested in that. In a warranty case, AMD could detect PLL programmings out of spec which would deny the warranty.
[*]Amato closed the session by mentioning Shanghai as a successor to Barcelona in the server space for 2008.[/li]
Shanghai will be an improved quad-core architecture, which is supposed to be socket-compatible with current Socket F platforms.
Shanghai is a 45nm quad-core CPU featuring 6MB of L3 Cache.
[*]the IMC can access memory in 64-bit channels (72-bit if you use ECC)[/li]
This way it is possible to read and write data simultaneously, or improve efficiency for irregular access patterns which increasingly occur in a quad-core environment
[*]Due to split power planes, the IMC can be clocked down independently of the CPU cores, along with reduced voltage[/li]
This also enables CPU overclocking without touching the memory frequency, something that may appeal to enthusiasts. These features are again dependent on Socket AM2+ and F+ platforms.
[*]quad-core design benefits from the internal crossbar switch the backbone of communication inside the K10 CPU. [/li]
With Intel's current quad-core design there are cases where data needs to travel over the FSB -- in AMDs case all inter-CPU communication takes place on-die.
[*]Amato also mentioned an array of power saving measures which, in sum, allow AMD to deliver a quad-core CPU in the same thermal envelope as today?s dual-core CPUs[/li]
[*]K10 adds the capability of independently clocking all the CPU cores.[/li]
This feature could possibly be abused by overclockers to overclock a single core above the specified levels. Amato clarified that AMD doesn't endorse overclocking, but acknowledges there are people interested in that. In a warranty case, AMD could detect PLL programmings out of spec which would deny the warranty.
[*]Amato closed the session by mentioning Shanghai as a successor to Barcelona in the server space for 2008.[/li]
Shanghai will be an improved quad-core architecture, which is supposed to be socket-compatible with current Socket F platforms.
Shanghai is a 45nm quad-core CPU featuring 6MB of L3 Cache.
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