Question AMD Rembrandt/Zen 3+ APU Speculation and Discussion

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izaic3

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Nov 19, 2019
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Alright, so we've had some leaks so far. I don't know if any of it's been confirmed yet, as it's pretty early, but here is what I've surmised so far (massive grain of salt of course):

If if turns out to have RDNA 2 and 12 CU, I could see iGPU performance potentially almost doubling over Cezanne.

If I've made any mistakes or gotten anything wrong, please let me know. I'd also love to hear more knowledgeable people weigh in on their expectations.
 
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moinmoin

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Jun 1, 2017
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particularly against zen2 in van gogh as I think that's also N6?
Van Gogh is N7. Even Dragon Crest appears to be N7 still.

There appears to be a distinct lack of designs on N6, Warhol may as well not exist, that leaves Rembrandt. Raphael and Phoenix are on N5 already.
 

tomatosummit

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Mar 21, 2019
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I think the product family number has more to do with compiler targets, although what exactly needs to change for a compiler to need a different target I don't know - off the top of my head I don't know what instruction set changes happened between Zen 1/+ and 2.

I think cache infrastructure plays some part in compiler targets too - anyone knowledgable please feel free to disabuse me of that 😅.
You might be on target with the compiler targets.
In the end product numbers are just numbers, a label given to various versions numbers etc.

I don't think there was much intruction difference between zen1/2 or even 3 but zen4 is pegged to have avx512 isn't it?
Cache layout was always my interpretation of the biggest outward change.
Zen1/2 are 4core ccx with point to point access between their l3 slices. Even moving to chiplets didn't change the layout beyond the serdes link between the actual silicon slabs. My favourite read on this was the raven ridge hot chips presendation (2019?) on how the data paths in zen arch is routed which is the same, although expanded on, even in naples/rome/milan.
Zen3 and assuming zen4 are 8core ccx with a twisted ring l3 access.
 
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soresu

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Dec 19, 2014
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Van Gogh is N7. Even Dragon Crest appears to be N7 still.

There appears to be a distinct lack of designs on N6, Warhol may as well not exist, that leaves Rembrandt. Raphael and Phoenix are on N5 already.
I'm thinking that they had a group think about what SKUs are most beneficial to their bottom line and prioritised them for N6, possibly a RDNA2 die or 2 might be on it I reckon.

Isn't Rembrandt N6 though?
 

moinmoin

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Isn't Rembrandt N6 though?
That's what I wrote, that leaves Rembrandt as the only design on N6.

This is curious since we have plenty indications that TSMC wants its customers to move from N7 to N6, but AMD's only N6 design is one that's also already has an N5 counterpart coming in Phoenix.
 
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tomatosummit

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That's what I wrote, that leaves Rembrandt as the only design on N6.

This is curious since we have plenty indications that TSMC wants its customers to move from N7 to N6, but AMD's only N6 design is one that's also already has an N5 counterpart coming in Phoenix.
It's something I brought up before but I'm curious about how much of rembrandt is using N6 libraries.
All the large blocks in it are already designed and verified on N7 (z3ccx, rdna2wgp, pcie4, data hubs)
I think it's a majority N7 design ported to N6 for performance characteristics.

I thought phoenix was zen4 plus rdna2/3 launching q1 2022? (edit=Q1 2023)
 
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ahimsa42

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Jul 16, 2016
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It's something I brought up before but I'm curious about how much of rembrandt is using N6 libraries.
All the large blocks in it are already designed and verified on N7 (z3ccx, rdna2wgp, pcie4, data hubs)
I think it's a majority N7 design ported to N6 for performance characteristics.

I thought phoenix was zen4 plus rdna2/3 launching q1 2022?

rembrandt zen3+/RDNA2 is rumored to be released in 1Q22-zen4 phoenix will not be out until 4Q 22 or 1Q 23.
 

soresu

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Dec 19, 2014
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I thought phoenix was zen4 plus rdna2/3 launching q1 2022? (edit=Q1 2023)
Yes.

Rumours initially put it as RDNA3 and then RDNA2.

I think RDNA2 could last a bit like Vega did in the APU space, at least in terms of the number of separate designs using it, which is already looking like 3 minimum (not counting Exynos).
 

Joe NYC

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Jun 26, 2021
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Van Gogh is N7. Even Dragon Crest appears to be N7 still.

There appears to be a distinct lack of designs on N6, Warhol may as well not exist, that leaves Rembrandt. Raphael and Phoenix are on N5 already.

I think I have seen rumors that Rembrandt is on N6.
 

Joe NYC

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That's what I wrote, that leaves Rembrandt as the only design on N6.

This is curious since we have plenty indications that TSMC wants its customers to move from N7 to N6, but AMD's only N6 design is one that's also already has an N5 counterpart coming in Phoenix.

The Zen 3 CCD is the biggest volume chip that could have benefited from N6. But going forward, AMD will be using a lot of N6:
- Rembrandt
- CDNA2
- Zen4 IO die
- Zen3 V-Cache (likely)
- Navi 33
- Navi 31, 32 MCD module
 
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Spicy

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Oct 5, 2021
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I think the product family number has more to do with compiler targets, although what exactly needs to change for a compiler to need a different target I don't know - off the top of my head I don't know what instruction set changes happened between Zen 1/+ and 2.

I think cache infrastructure plays some part in compiler targets too - anyone knowledgable please feel free to disabuse me of that 😅.
You are right, I've seen several news on this:
AMD Zen 2 "znver2" Support Lands In LLVM Clang 9.0
AMD Zen 2 Improvements For LLVM Have Been Held Up For Months By Code Review
AMD Sends Out Patches Adding "Znver3" Support To GNU Binutils With New Instructions
A small window on everything that's going on. :)
 

Spicy

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Oct 5, 2021
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Last rumorts suggest that Raphael will be launched at the end of Q2 ~ beginning of Q3 (instead end of Q4). Any impact on the launch of DIY Rembrandt?
(see the screenshot)
 

soresu

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Dec 19, 2014
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Last rumorts suggest that Raphael will be launched at the end of Q2 ~ beginning of Q3 (instead end of Q4). Any impact on the launch of DIY Rembrandt?
(see the screenshot)
Who knows?

Perhaps with Raphael having GCD SKUs it may be that Rembrandt doesn't actually have an AM5 release at all.

Leaving Rembrandt for BGA NUC/SFF, embedded and mobile.
 

Spicy

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Oct 5, 2021
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Raphael's iGPU is too small for it to have it's own GCD

Might as well just call it an I/O die.
Yes, I already posted that, early plans of AMD was to integrate it on its IODie. I don't think that sketch has changed since then.
Very small gpu (if the drawing is to scale. of course, not).

I think the Chinese guy is confusing Raphael with Rembrandt.
With the Intel/ADL pressure, it make sense that AMD would try to bring forward the launch of its Zen 4.
 
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Asterox

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Yes.

Rumours initially put it as RDNA3 and then RDNA2.

I think RDNA2 could last a bit like Vega did in the APU space, at least in terms of the number of separate designs using it, which is already looking like 3 minimum (not counting Exynos).

iGPU performance, for example "only 8CU RDNA2+DDR5" will run over Vega 8CU iGPU+DDR4 combination.

Renoir Vega iGPU, it is not the same poor old Desktop GPU Vega but again very similar story.If Renoir/Cezanne could use DDR5, iGPU performance would be much better=more FPS.
 

tamz_msc

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Jan 5, 2017
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